MPM54504

– 16V, QUAD 5A, POWER MODULE

MPM54504 Rev. 1.0

MonolithicPower.com

13

3/19/2021

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© 2021 MPS. All Rights Reserved.

When the input voltage exceeds the UVLO rising

threshold voltage, the MPM54504 powers up.

The device shuts down when the input voltage

drops below the UVLO falling threshold voltage.

This is non-latch protection.

Soft Start

The MPM54504 employs a soft start (SS)

mechanism to ensure the output ramps smoothly

during start-up. When the EN pin goes high, an

internal current source (6µA) charges the SS

capacitor. During soft start, the soft start voltage

works instead of VFB. The output voltage

smoothly ramps up with the SS voltage. Once

the SS voltage (VSS) rises above VREF, VREF takes

over. At this point, soft start is completed, and

the device enters steady state operation.

The SS capacitor value (CSS) can be calculated

with Equation (1):

SS

SS

SS

REF

t (ms) I ( A)

C (nF)=0.83

V

(V)





(1)

Ensure that the SS time is not too short if the

output capacitance is large. A large capacitance

can prevent the current limit from being reached

during soft start.

Power Good (PG) Indicator

The PG pin is the open drain of a MOSFET that

is connected to VCC (or another voltage source)

through a resistor (e.g. 100kΩ). The MOSFET

turns on when an input voltage is applied, so that

the PG pin is pulled to GND before SS is ready.

After the FB voltage (VFB) reaches 90% of VREF,

the PG pin is pulled high after a 50µs delay.

When VFB drops to 80% of VREF, the PG pin is

pulled low.

If

under-voltage

lockout

(UVLO)

or

over-

temperature protection (OTP) occurs, the PG pin

is pulled low immediately. If an over-current (OC)

condition occurs, the PG pin is pulled low when

VFB drops below 80% of VREF after a 50µs delay.

If an over-voltage (OV) condition occurs, the PG

pin is pulled low when VFB rises above 120% of

VREF after a 50µs delay. If VFB drops below 110%

of VREF, the PG pin is pulled high after a 50µs

delay.

If the input supply fails to power the MPM54504,

PG is clamped low, even if PG is tied to an

external DC source through a pull-up resistor.

Figure 4 shows the relationship between the PG

voltage and the pull-up current.

Figure 5: PG Clamped Voltage vs. Pull-Up

Current

Over-Current Protection (OCP) and Short-

Circuit Protection (SCP)

The MPM54504 has valley current limit control.

The LS-FET monitors the current flowing through

the LS-FET. The HS-FET does not turn on until

the valley current limit disappears. An under-

voltage (UV) condition is triggered if VFB drops

below the UV threshold (typically below 50% of

VREF). Once UVP is triggered, the MPM54504

enters hiccup mode to periodically restart the

part.

During over-current protection (OCP), the device

tries to recover from the OC fault with hiccup

mode. This means that the chip disables the

output power stage and soft-start capacitor, then

automatically tries to initiate a soft start. If the OC

condition remains after soft start ends, the

device repeats this operation until the OC

condition is removed. Then the output rises back

to the regulated voltage. OCP is a non-latch

protection.

Pre-Biased Start-Up

The

MPM54504

has

been

designed

for

monotonic start-up into pre-biased loads. If the

output is pre-biased to a certain voltage during

start-up, the BST voltage is refreshed and

charged, and the voltage on the soft-start

capacitor is also charged. If the BST voltage

exceeds its rising threshold voltage and the soft-

start capacitor voltage exceeds the sensed

output voltage at the FB pin, the part starts to

work normally.