MPM54504

– 16V, QUAD 5A, POWER MODULE

MPM54504 Rev. 1.0

MonolithicPower.com

16

3/19/2021

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



 



 

OUT

OUT

OUT

2

SW

OUT

IN

VV

V

(1

)

8 f

L C

V

(8)If

using POSCAP capacitors, the ESR dominates

the impedance at the switching frequency. For

simplification, the output ripple can be estimated

with Equation (9):





 





OUT

OUT

OUT

ESR

SW

IN

VV

V

(1

) R

f

L

V

(9)

In addition to considering the output ripple, a

larger-value output capacitor improves the load

transient response. However, the maximum

output capacitor limit should be also considered

in design applications. If the output capacitor

value is too high, the output voltage cannot reach

the design value during the soft-start time, and

the device fails to regulate. The maximum output

capacitor value (CO_MAX) can be calculated using

Equation (10):







O _MAX

LIM_ AVG

OUT

ss

OUT

C

(I

I

) t / V

(10)

Where ILIM_AVG is the average start-up current

during soft start, and tSS is the soft-start time.

PCB Layout Guidelines

The PCB layout is critical for stable operation. A

6-layer layout is recommended to improve

thermal performance. For the best results, refer

to Figure 7 and follow the guidelines below:

1. Keep the power loop as small as possible.

2. Use a large ground plane to connect directly

to PGND. Add as many vias as possible on

the PGND plane, and near the device to

improve thermal performance.

3. Ensure that the high-current paths at GND

and VIN have short, direct, and wide traces.

4. Place the ceramic input capacitor, especially

capacitors with a small package size (0402),

as close to the VIN and PGND pins as

possible to minimize high-frequency noise.

Keep the input capacitor and VIN pin traces

as short and wide as possible.

5. Place the VCC capacitor as close to the VCC

pin and GND as possible.

6. Do not place the GND plane under the device.

2

1

A3

B3

C3

D3

E3

2

1

2

1

2

1

2

1

VOUT4

VOUT2

VOUT1

GND

VIN

2

1

2

1

2

1

2

1

VOUT3

VIN

VOUT1

VOUT2

VOUT3

VOUT4

GND

Vias

GND

GND

Figure 7: Recommended PCB Layout