UPD78P014 datasheet(38/64 Pages) RENESAS

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µPD78P014

Parameter

SCK cycle time

SCK high/low-level

width

SI setup time (to SCK

↑)

SI hold time (from SCK

↑)

SO output delay time

from SCK

↓

(g)

3-wire serial I/O mode with automatic transmit/receive function (SCK...Internal clock output)

MIN.

TYP.

MAX.

Unit

800

3200

tKCY7/2 – 50

tKCY7/2 – 150

100

400

300

1000

400

tKCY7

tKCY7 – 30

tKCY7 + 30

100

2tKCY7

Test Conditions

VDD = 4.5 to 6.0 V

Note

VDD = 4.5 to 6.0 V

C = 100 pF

Symbol

tKCY7

tKH7

tKL7

tSIK7

tKSI7

tKSO7

tSBD

tSBW

tBYS

tBYH

tSPS

Parameter

SCK cycle time

SCK high/low-level

width

SI setup time (to SCK

↑)

SI hold time (from SCK

↑)

SO output delay time

from SCK

↓

STB

↑ from SCK↑

Strobe signal high-

level width

Busy signal setup time

(to busy signal

detection timing)

Busy signal hold time

(from busy signal

detection timing)

SCK

↓ from busy

inactive

Note C is the load capacitance of the SO output line.

(h)

3-wire serial I/O mode with automatic transmit/receive function (SCK...External clock input)

MIN.

TYP.

MAX.

Unit

800

3200

400

1600

100

400

300

1000

Symbol

tKCY8

tKH8

tKL8

tSIK8

tKSI8

tKSO8

Test Conditions

VDD = 4.5 to 6.0 V

Note

VDD = 4.5 to 6.0 V

C = 100 pF

When using the external device

expansion function

When not using the external

device expansion function

160

1000

tR8

tF8

SCK rise and fall times

Note C is the load capacitance of the SO output line.

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