UPD78P014 datasheet(37/64 Pages) RENESAS

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µPD78P014

Test Conditions

VDD = 4.5 to 6.0 V

R = 1 k

Ω, C = 100 pFNote

R = 1 k

Ω,

VDD = 4.5 to 6.0 V

C = 100 pFNote

Symbol

tKCY5

tKH5

tKL5

tSIK5

tKSI5

tKSO5

Parameter

SCK cycle time

SCK high-level width

SCK low-level width

SB0, SB1 setup time (to SCK

↑)

SB0, SB1 hold time (from SCK

↑)

SB0, SB1 output delay time

from SCK

↓

When not

using the

external device

expansion

function

When using the external device

expansion function

When using the

16-bit timer

output function

When not using

the 16-bit timer

output function

Test Conditions

VDD = 4.5 to 6.0 V

R = 1 k

Ω,

VDD = 4.5 to 6.0 V

C = 100 pFNote

Symbol

tKCY6

tKH6

tKL6

tSIK6

tKSI6

tKSO6

Parameter

SCK cycle time

SCK high-level width

SCK low-level width

SB0, SB1 setup time (to SCK

↑)

SB0, SB1 hold time (from SCK

↑)

SB0, SB1 output delay time

from SCK

↓

(e)

2-wire serial I/O mode (SCK... Internal clock output)

Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line.

(f)

2-wire serial I/O mode (SCK... External clock input)

Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line.

MIN.

TYP.

MAX.

Unit

1600

3800

650

800

100

tKCY6/2

300

1000

SCK rise and fall times

tR6

tF6

160

700

1000

MIN.

TYP.

MAX.

Unit

1600

3800

tKCY5/2 – 50

300

600

250

1000

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