UPD75P4308GS datasheet(44/61 Pages) RENESAS

tên linh kiện	UPD75P4308GS

Giải thích chi tiết về linh kiện	MOS INTEGRATED CIRCUIT

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µPD75P4308

Data Sheet U10909EJ2V1DS

Interrupt input timing

INT0, 1, 2, 4

KR0-7

tINTL

tINTH

RESET input timing

RESET

tRSL

Data retention characteristics of data memory in STOP mode and at low supply voltage

(TA = –40 to +85˚C)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Release signal set time

tSREL

µs

Oscillation stabilization

tWAIT

Released by RESET

215/fx

wait timeNote 1

Released by interrupt request

Note 2

Notes 1. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent

unstable operation when oscillation is started.

2. Set by the basic interval timer mode register (BTM). (Refer to the table below.)

BTM3

BTM2

BTM1

BTM0

Wait time

fX = 4.19 MHz

fX = 6.0 MHz

–000

220/fX (approx. 250 ms)

220/fX (approx. 175 ms)

–011

217/fX (approx. 31.3 ms)

217/fX (approx. 21.8 ms)

–101

215/fX (approx. 7.81 ms)

215/fX (approx. 5.46 ms)

–111

213/fX (approx. 1.95 ms)

213/fX (approx. 1.37 ms)

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