LXT6155LE datasheet(27/50 Pages) INTEL

27 / 50 page

Datasheet

155 Mbps SDH/SONET/ATM Transceiver — LXT6155

Table 8.

Primary Control Register Settings, Register #0 (Address A<3:0>=0000)

Bit

Default

Mnemonic

Description

lpbk_cntl

Local loopback:

0 = No loopback

1 = Activate local loopback

Remote loopback:

0 = No loopback

1 = Activate remote loopback

pll_ref

PLL/Equalizer reference clock control:

0= UseTPICLK clock

1 = Use external crystal (XTALIN)

Not used

clk_inv

TPICLK polarity at system interface:

0= TPID <7:0>sampled on therisingedgeof TPICLK

1 = TPID <7:0> sampled on the falling edge of TPICLK

RPOCLK polarity at system interface:

0 = RPOD <7:0> transitions on the rising edge of RPOCLK

1 = RPOD <7:0> transitions on the falling edge of RPOCLK

sys_int

Systems interface mode selection:

0 = Serial mode

1 = Parallel 8 bit mode

media_sel

Media and line code selection:

0 = Fiber (NRZ)

1= Coax (CMI)

Table 9.

Tx Control, Register #1 (Address A<3:0>=0001)

Bit

Default

Mnemonic

Description

tx_ena

Tx output enable:

0 = outputs disabled

1 = outputs active

tx_dig_reset

Tx digital circuitry reset. This can be used to minimize power comsumption when

the device is disabled but not powered down. It must be enabled when the device

is active.

0= reset

1= active

4:1

0.1.1.1

tx_amp_trim

Transmit amplitude trim:

0000 = -21%

1111 = +24%

tx_clk_sw_ena

Tx clock detection enable. This must be disabled in SW mode when pll_ref=0

(reg#0<5>=0)

0= disable

1 = enable

LXT6155LE bảng dữ liệu(PDF) 27 Page - Intel Corporation

LXT6155LE bảng dữ liệu(HTML) 27 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

bảng dữ liệu tải về

Link URL