CS4525 datasheet(48/91 Pages) CIRRUS

48 / 91 page

DS726A1

CS4525

6.1.9

Interrupt Reporting

The CS4525 has comprehensive interrupt reporting capabilities. Many conditions including SRC lock,

ADC overflow, digital data path overflow, and amplifier errors can cause an interrupt.

The INT output pin is intended to drive an interrupt input pin on a host microcontroller. The INT pin is an

open-drain active-low output and requires an external pull-up for proper operation.

If an interrupt source is un-masked, its occurrence will cause the interrupt output pin to become active. To

enhance flexibility, each interrupt source may be masked such that its occurrence does not cause the in-

terrupt output pin to become active. This masking function is accomplished by clearing an interrupt’s re-

spective mask bit located in the 4 LSB’s of the Interrupt register.

When a specific interrupt condition occurs, it’s respective bit located in the 4 MSB’s of the Interrupt register

will be set to indicate that a change has occurred for the associated interrupt type. When the interrupt reg-

ister is read, the contents of the 4 MSB’s will be cleared. The Int Status register may then be read to de-

termine the current state of the interrupt source.

For specific information regarding interrupt types and reporting, see the Interrupt, Int Status and Amp Er-

ror register descriptions.

6.1.10

Automatic Power Stage Shut-Down

To prevent permanent damage, the CS4525 will automatically shut down its internal PWM power output

stages when a thermal error, PWM power output over-current error, or VP under-voltage condition occurs.

In the shut-down state, all digital functions of the device will operate as normal, however the PWM power

output pins become high-impedance.

The levels of the over-current error, thermal error, and VP under-voltage trip points are listed in the PWM

Power Output Characteristics table on page 20. Automatic shut-down will occur whenever any of these

preset thresholds are crossed.

Once in the shut-down state, the PDnAll bit in the Power Ctrl register must be set and then cleared to

resume normal device operation.

Referenced Control

Interrupt Register ................ “Interrupt Register (Address 60h)” on page 82

Int Status Register............... “Interrupt Status Register (Address 61h) - Read Only” on page 84

Amp Error Register ............. “Amplifier Error Status (Address 62h) - Read Only” on page 85

Referenced Control

PDnAll ................................. “Power Down (PDnAll)” on page 81

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