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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v1-00 • 2020-Dec-15

112

│ 49

Information

The top and bottom output channels are not aligned. The user should use the top side clock and

control channels to evaluate the top data channels, and the bottom side clock and control channels

to evaluate the bottom data channels.

The data on the control channel contains status information on the validity of the data on the data

channels, along with status information on the sensor state. Information on the control channel is

grouped into 12-bit words that are transferred synchronous to the data channels.

The figure below shows the data output interface.

Figure 51:

Sub-LVDS Data Output Interface

Each pair of differential output pins transports data on one sub-LVDS channel.

For easier reading and writing, the channels will be called CTR_OUT, DATAx_OUT, OB_OUT and

CLK_OUT in the remainder of the document. The output channels have the following functionality:

Figure 52:

Sub-LVDS Output Channels Functionality

Name

Function

CLK_OUT

Should be used as sampling clock.

CTR_OUT

Serially transmit status word. Captures sensor status and data validity in various status bits.

...

CTR_OUT

(BOTTOM)

CLK_OUT

(BOTTOM)

DATA0_OUT

(BOTTOM)

DATA1_OUT

(BOTTOM)

OB_OUT

(BOTTOM)

DATA7_OUT

(BOTTOM)

...

CTR_OUT

(TOP)

CLK_OUT

(TOP)

DATA0_OUT

(TOP)

DATA1_OUT

(TOP)

OB_OUT

(TOP)

DATA7_OUT

(TOP)

...

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