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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v1-00 • 2020-Dec-15

112

│ 16

Functional Description

7.1

Sensor Architecture

Figure 2 shows a high-level representation of the chip architecture for the CSG14K_CSG8K sensor.

The drawing shows the pixel array and the periphery around it that enables the control and readout of

the pixels.

The core of the image sensor is made up from the pixel array, which is driven from two sides through

row logic and drivers. The pixel data is read out, row by row, using a data path consisting of an sample

and hold stage (S&H), analog-to-digital converter (ADC) and a digital data post-processing (DPP)

block. The top part of the pixel array is read out via the top outputs, while the bottom part is read via

the bottom outputs.

The converted data is sent, pixel by pixel, to a configurable number of data output channels. An

additional control (CTR) channel provides synchronization information about the data on the data

channels, while a specific CLK channel can be used to sample the data channels.

An optional output channel allows reading out OB pixel columns on the right side of the pixel array.

The on-chip PLL transforms a low-frequency CMOS input clock into all the high frequency clocks

needed to operate the sensor.

An on-chip sequencer controls the sensor operation and contains SPI programmable registers.

Two on-chip temperature sensors and an OTP memory are available.

7.1.1

Pixel Array

This section is split-up between CSG14K and CSG8K. The pixel array of the CSG8K is very similar to

the pixel array of the CSG14K, except that some rows cannot be read out to limit vertical resolution in

CSG8K. Refer to chapter 7.5.3 for more details on which rows can be addressed.

Pixel Array of the CSG14K

Figure 11 shows the complete pixel array.

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