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CS53L21 bảng dữ liệu(PDF) 29 Page - Cirrus Logic

tên linh kiện CS53L21
Giải thích chi tiết về linh kiện  Low Power, Stereo Analog to Digital Converter
PDF  66 Pages
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nhà sản xuất  CIRRUS [Cirrus Logic]
Trang chủ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS53L21 bảng dữ liệu(HTML) 29 Page - Cirrus Logic

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DS700PP1
29
CS53L21
4.5
Serial Port Clocking
The A/D serial audio interface port operates either as a slave or master. It accepts externally generated
clocks in slave mode and will generate synchronous clocks derived from an input master clock (MCLK) in
master mode.
The frequency of the MCLK must be an integer multiple of, and synchronous with, the system sample rate,
Fs. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked
into or out of the device.
The SPEED and MCLKDIV2 software control bits or the SDOUT/(M/S) and MCLKDIV2 stand-alone control
pins, configure the device to generate the proper clocks in Master Mode and receive the proper clocks in
Slave Mode. The value on the SDOUT pin is latched immediately after powering up in Hardware Mode.
Software
Control:
“MIC Power Control & Speed Control (Address 03h)” on page 41, “SPE Control
(Address 09h)” on page 48.
Hardware
Control:
Pin
Setting
Selection
“SDOUT, M/S” pin 29
47 k
Ω Pull-down
Slave
47 k
Ω Pull-up
Master
“MCLKDIV2” pin 2
LO
No Divide
HI
MCLK is divided by 2 prior
to all internal circuitry.



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