TMD3702VC datasheet(36/57 Pages) AMSCO

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Datasheet, Public

Page 35

[v2-00] 2023-Mar-14

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TMD3702VC − Register Description

CFG3 Register (Address 0xAB)

Figure 54:

CFG3 Register

The SAI bit sets the device operational mode following the

completion of an ALS or proximity cycle. If AINT and AIEN are

both set or if PINT and PIEN are both set, causing an interrupt

on the INT pin, and the SAI bit is set, then the oscillator will

deactivate. The device will appear as if PON = 0, however, PON

will read as 1. The device can only be reactivated (oscillator

enabled) by clearing the interrupts in the STATUS register.

CFG4 Register (Address 0xAC)

Figure 55:

CFG4 Register

Addr: 0xAB

CFG3

Bit

Bit Name

Default

Access

Bit Description

INT_READ_CLEAR

If set, then all flag bits in the STATUS register will be

reset whenever the STATUS register is read over I²C.

6:5

Reserved

Reserved. Must be set to default value.

4SAI

The Sleep After Interrupt bit is used to place the

device into a low power mode upon an interrupt pin

assertion.

PON

SAI

INT

Oscillator

OFF

3:0

Reserved

0100

Reserved. Must be set to default value.

Addr: 0xAC

CFG4

Bit

Bit Name

Default

Access

Bit Description

7:0

Reserved

0x3F

Reserved. Must be set to 0x3D.

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