AD8190ACPZ-R7 datasheet(22/24 Pages) AD

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AD8190

Rev. 0 | Page 22 of 24

Power Supply Bypassing

The AD8190 requires minimal supply bypassing. When

powering the supplies individually, place a 0.01 μF capacitor

between each 3.3 V supply pin (AVCC, DVCC, VTTI, and

VTTO) and ground to filter out supply noise. Generally, bypass

capacitors should be placed near the power pins and should

connect directly to the relevant supplies (without long inter-

vening traces). For example, to improve the parasitic inductance

of the power supply decoupling capacitors, minimize the trace

length between capacitor landing pads and the vias as shown in

Figure 34.

EXTRA ADDED INDUCTANCE

RECOMMENDED

NOT RECOMMENDED

Figure 34. Recommended Pad Outline for Bypass Capacitors

In applications where the AD8190 is powered by a single 3.3 V

supply, it is recommended to use two reference supply planes

and bypass the 3.3 V reference plane to the ground reference

plane with one 220 pF, one 1000 pF, two 0.01 μF, and one 4.7 μF

capacitors. The capacitors should via down directly to the

supply planes and be placed within a few centimeters of the

AD8190. The AMUXVCC supply does not require additional

bypassing. This scheme is illustrated in Figure 35.

DECOUPLING

CAPACITORS

AUXILIARY LINES

TMDS TRACES

AD8190

Figure 35. Example Placement of Power Supply Decoupling Capacitors

Around the AD8190

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