P87LPC778FDH datasheet(14/79 Pages) PHILIPS

14 / 79 page

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data

Rev. 01 — 31 March 2004

14 of 79

9397 750 12378

8.4 A/D timing

The A/D may be clocked in one of two ways. The default is to use the CPU clock as

the A/D clock source. When used in this manner, the A/D completes a conversion in

31 machine cycles. The A/D may be operated up to the maximum CPU clock rate of

20 MHz, giving a conversion time of 9.3

µs. The formula for calculating A/D

conversion time when the CPU clock runs the A/D is: 186

µs / CPU clock rate

(in MHz). To obtain accurate A/D conversion results, the CPU clock must be at least

1 MHz.

The A/D may also be clocked by the on-chip RC oscillator, even if the RC oscillator is

not used as the CPU clock. This is accomplished by setting the RCCLK bit in

ADCON. This arrangement has several advantages. First, the A/D conversion time is

faster at lower CPU clock rates. Also, the CPU may be run at speeds below 1 MHz

without affecting A/D accuracy. Finally, the Power-down mode may be used to

completely shut down the CPU and its oscillator, along with other peripheral

functions, in order to obtain the best possible A/D accuracy.

When the A/D is operated from the RCCLK while the CPU is running from another

clock source, 3 or 4 machine cycles are used to synchronize A/D operation. The time

can range from a minimum of 3 machine cycles (at the CPU clock rate) + 108 RC

clocks to a maximum of 4 machine cycles (at the CPU clock rate) + 112 RC clocks.

Example A/D conversion times at various CPU clock rates are shown in Table 8. In

the table, maximum times for RCCLK = 1 use an RC clock frequency of 6 MHz.

Minimum times for RCCLK = 1 use an RC clock frequency of. Nominal time assume

an ideal RC clock frequency of 6 MHz and an average of 3.5 machine cycles at the

CPU clock rate.

Table 6:

ADCON - ADCI, ADCS A/D status

ADCI, ADCS

A/D status

0 0

A/D not busy, a conversion can be started

0 1

A/D busy, the start of a new conversion is blocked.

1 0

An A/D conversion is complete. ADCI must be cleared prior to starting a

new conversion.

1 1

An A/D conversion is complete. ADCI must be cleared prior to starting a

new conversion. This state exists for one machine cycle as an A/D

conversion is completed.

Table 7:

ADCON - AADR1, AADR0 A/D input selection

AADR1, AADR0

A/D input selected

0 0

AD0 (P0.3)

0 1

AD1 (P0.4)

1 0

AD2 (P0.5)

1 1

AD3 (P0.6)

P87LPC778FDH bảng dữ liệu(PDF) 14 Page - NXP Semiconductors

P87LPC778FDH bảng dữ liệu(HTML) 14 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

bảng dữ liệu tải về

Link URL