P87LPC778FDH datasheet(45/79 Pages) PHILIPS

45 / 79 page

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data

Rev. 01 — 31 March 2004

45 of 79

9397 750 12378

8.13 Reset

The P87LPC778 has an active LOW reset input when conﬁgured for an external

reset. A fully internal reset may also be conﬁgured which provides a reset when

power is initially applied to the device. The Watchdog timer can act as an oscillator fail

detect because it uses an independent, fully on-chip oscillator.

The external reset input is disabled, and fully internal reset generation enabled, by

programming the RPD bit in the EPROM conﬁguration register UCFG1 to 0. EPROM

conﬁguration is described in Section 8.18 “EPROM characteristics” on page 66.

POF

Power-on Flag. Set automatically when a Power-on reset has

occurred. Cleared by software. Refer to the Section 8.11 “Power

monitoring functions” on page 42 for additional information.

GF1

General purpose ﬂag 1. May be read or written by user software,

but has no effect on operation.

GF0

General purpose ﬂag 0. May be read or written by user software,

but has no effect on operation.

Power-down control bit. Setting this bit activates Power-down

mode operation. Cleared when the Power-down mode is

terminated (see text).

IDL

Idle mode control bit. Setting this bit activates Idle mode operation.

Cleared when the Idle mode is terminated (see text).

Table 42:

PCON - Power control register (address 87H) bit description…continued

Bit

Symbol

Description

Fig 17. Typical external reset circuits.

002aaa635

87LPC778

P1.5

87LPC778

RST

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