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DP83849IF bảng dữ liệu(PDF) 74 Page - National Semiconductor (TI)

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tên linh kiện DP83849IF
Giải thích chi tiết về linh kiện  PHYTER짰 DUAL Industrial Temperature with Fiber Support (FX) an Flexible Port Switching Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver
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7.2.7 10 Base-T Status/Control Register (10BTSCR)
This register is used for control and status for 10BASE-T device operation.
6
5
LED_CNFG[1]
LED_CNFG[0]
0, RW
Strap, RW
LED Configuration
In Mode 1, LEDs are configured as follows:
LED_LINK = ON for Good Link, OFF for No Link
LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s
LED_ACT/LED_COL = ON for Activity, OFF for No Activity
In Mode 2, LEDs are configured as follows:
LED_LINK = ON for good Link, BLINK for Activity
LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s
LED_ACT/LED_COL = ON for Collision, OFF for No Collision
Full Duplex, OFF for Half Duplex
In Mode 3, LEDs are configured as follows:
LED_LINK = ON for Good Link, BLINK for Activity
LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s
LED_ACT/LED_COL = ON for Full Duplex, OFF for Half Duplex
4:0
PHYADDR[4:0]
Strap, RW
PHY Address: PHY address for port.
Table 39. 10Base-T Status/Control Register (10BTSCR), address 1Ah
Bit
Bit Name
Default
Description
15
10BT_SERIAL
Strap, RW
10Base-T Serial Mode (SNI)
1 = Enables 10Base-T Serial Mode
0 = Normal Operation
Places 10 Mb/s transmit and receive functions in Serial Network
Interface (SNI) Mode of operation. Has no effect on 100 Mb/s
operation.
14:12
RESERVED
0, RW
RESERVED:
Must be zero.
11:9
SQUELCH
100, RW
Squelch Configuration:
Used to set the Squelch ‘ON’ threshold for the receiver.
Default Squelch ON is 330mV peak.
Table 38. PHY Control Register (PHYCR), address 19h (Continued)
Bit
Bit Name
Default
Description
LED_CNFG[1]
LED_ CNFG[0]
Mode Description
Don’t care
1
Mode 1
00
Mode 2
10
Mode 3



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