MC68340 datasheet(206/441 Pages) FREESCALE

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MOTOROLA

MC68340 USER’S MANUAL

5- 69

The serial interface uses a full-duplex synchronous protocol similar to the serial peripheral

interface (SPI) protocol. The development system serves as the master of the serial link

since it is responsible for the generation of DSCLK. If DSCLK is derived from the CPU32

system clock, development system serial logic is unhindered by the operating frequency of

the target processor. Operable frequency range of the serial clock is from DC to one-half

the processor system clock frequency.

The serial interface operates in full-duplex mode—i.e., data is transmitted and received

simultaneously by both master and slave devices. In general, data transitions occur on the

falling edge of DSCLK and are stable by the following rising edge of DSCLK. Data is

transmitted MSB first and is latched on the rising edge of DSCLK.

The serial data word is 17 bits wide—16 data bits and a status/control (S/C) bit.

S/C

DATA FIELD

Bit 16 indicates the status of CPU-generated messages as shown in Table 5-21.

Table 5-21. CPU Generated Message Encoding

Encoding

Data

Message Type

xxxx

Valid Data Transfer

FFFF

Command Complete; Status OK

0000

Not Ready with Response; Come Again

0001

BERR Terminated Bus Cycle; Data Invalid

FFFF

Illegal Command

Command and data transfers initiated by the development system should clear bit 16. The

current implementation ignores this bit; however, Motorola reserves the right to use this bit

for future enhancements.

5.6.2.7.1 CPU Serial Logic. CPU serial logic, shown in the left-hand portion of Figure 5-

22, consists of transmit and receive shift registers and of control logic that includes

synchronization, serial clock generation circuitry, and a received bit counter.

Both DSCLK and DSI are synchronized to on-chip clocks, thereby minimizing the chance

of propagating metastable states into the serial state machine. Data is sampled during the

high phase of CLKOUT. At the falling edge of CLKOUT, the sampled value is made

available to internal logic. If there is no synchronization between CPU32 and development

system hardware, the minimum hold time on DSI with respect to DSCLK is one full period

of CLKOUT.

Freescale Semiconductor, Inc.

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