ST7789V2 datasheet(121/319 Pages) SITRONIX

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ST7789V2

Version 1.0

Page 121 of 319

2016/11

Sitronix Confidential

The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or

disclosed in whole or in part without prior written permission of Sitronix.

Display operation can be achieved by using the internal clock generated by the internal oscillator and the

VSYNC input. Because all the data for display is written to RAM, only the data to be rewritten is transferred.

This method reduces the amount of data transferred during motion picture display operation.

Write Data to

Frame Memory

Source

Gate320

Gate1

Gate2

D[17:0]

1 Line

Figure 29 Timing Diagram of VSYNC Interface

VSYNC interface requires taking the minimum speed for RAM writing via the system interface and the

frequency of the internal clock into consideration. RAM writing should be performed with higher speed than

the result obtained from the calculation shown below. The internal memory writing address counter is reset by

VSYNC. So, insure interval time between VSYNC falling and DRAM data writing.

Note:

1. VSYNC period should always be constant. If not, some degradation of display such as flicker may occur in LCD system.

2. Display data don’t need to be written for every VSYNC period. For example, any system is working under 60Hz frame rate and

30-fps motion picture condition. So being written display data for every other frame would be enough.

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