ICSSSTUAF32868B

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

COMMERCIAL TEMPERATURE GRADE

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

19

ICSSSTUAF32868B

7102/2

Test Circuits and Waveforms (VDD = 1.8V ± 0.1V)

Load Circuit: High-to-Low Slew-Rate Adjustment

Voltage Waveforms: High-to-Low Slew-Rate Adjustment

Load Circuit: Low-to-High Slew-Rate Adjustment

Voltage Waveforms: Low-to-High Slew-Rate Adjustment

Load Circuit: Error Output Measurements

Voltage Waveforms: Open Drain Output Low-to-High

Transition Time (with respect to RESET input)

Voltage Waveforms: Open Drain Output High-to-Low

Transition Time (with respect to clock inputs)

Voltage Waveforms: Open Drain Output Low-to-High

Transition Time (with respect to clock inputs)

NOTES:

1. CL includes probe and jig capacitance.

2. All input pulses are supplied by generators having the following characteristics: PRR

≤10MHz, Zo = 50Ω, input

slew rate = 1 V/ns ±20% (unless otherwise specified).

CL =10 pF

RL =50

Ω

DUT

Out

Test Point

VDD

VOH

80%

20%

VOL

Output

dv_f

dt_f

CL =10pF

RL =50

Ω

DUT

Out

Test Point

VOL

20%

80%

VOH

Output

dv_r

dt_r

CL =10 pF

RL =1K

Ω

DUT

Out

Test Point

VDD

VOH

VCC

Output

Waveform 2

LVCMOS

RESET

Input

tPLH

VCC/2

0.15V

0V

0V

VCC

VICR

tHL

Timing

Inputs

VICR

VI(PP)

Output

Waveform 1

VCC/2

VOL

VOH

Output

Waveform 2

0.15V

0V

VICR

tHL

Timing

Inputs

VICR

VI(PP)