ICSSSTUAF32868B datasheet(11/23 Pages) RENESAS

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ICSSSTUAF32868B

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

COMMERCIAL TEMPERATURE GRADE

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32868B

7102/2

Terminal Functions

Terminal Name

Electrical

Characteristics

Description

GND

Ground Input

Ground

VDD

1.8V nominal

Power Supply Voltage

VREF

0.9V nominal

Input Reference Clock

CLK

Differential Input

Positive Master Clock Input

CLK

Differential Input

Negative Master Clock Input

LVCMOS Input

Configuration Control Inputs - Register A or Register B

RESET

LVCMOS Input

Asynchronous Reset Input. Resets registers and disables Vref data

and clock differential-input receivers.

CSGEN

LVCMOS Input

Chip select gate enable – When high, D1-D28 inputs will be latched

only when at least one chip select input is low during the rising edge

of the clock. When low, the D1-D28 inputs will be latched and

redriven on every rising edge of the clock.

D1 - D28

SSTL_18 Input

Data Input. Clocked in on the crossing of the rising edge of CLK

and the falling edge of CLK.

DCS0, DCS1

SSTL_18 Input

Chip select inputs – These pins initiate DRAM address/command

decodes, and as such at least one will be low when a valid

address/command is present. The Register can be programmed to

redrive all D inputs (CSGEN high) only when at least one chip select

input is low. If CSGEN, DCS0, and DCS1 inputs are high, D1-D28

inputs will be disabled.

DCKE0, DCKE1

SSTL_18 Input

The outputs of this register bit will not be suspended by the DCS0

and DCS1 controls

DODT0, DODT1

SSTL_18 Input

The outputs of this register bit will not be suspended by the DCS0

and DCS1 controls

PAR_IN

SSTL_18 Input

Parity Input arrives one cycle after corresponding data input

Q1 - Q28

1.8V CMOS

Data Outputs that are suspended by the DCS0 and DCS1 controls

QCS0, QCS1

1.8V CMOS

Data Output that will not be suspended by the DCS0 and DCS1

controls

QCKE0, QCKE1

1.8V CMOS

Data Output that will not be suspended by the DCS0 and DCS1

controls

QODT0, QODT1

1.8V CMOS

Data Output that will not be suspended by the DCS0 and DCS1

controls

QERR

Open Drain Output

Output Error bit, generated one cycle after the corresponding data

output

No Connection

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