CD4052BM datasheet(25/48 Pages) TI

25 / 48 page

9.2.2 Detailed Design Procedure

1. Recommended Input Conditions:

• For switch time specifications, see propagation delay times in Electrical Characteristics.

• Inputs should not be pushed more than 0.5 V above VDD or below VEE.

• For input voltage level specifications for control inputs, see VIH and VIL in Electrical Characteristics.

2. Recommended Output Conditions:

• Outputs should not be pulled above VDD or below VEE.

3. Input or output current consideration:

• The CD405xB series of parts do not have internal current drive circuitry and thus cannot sink or source

current. Any current will be passed through the device.

9.2.3 Application Curve

-6

-4

-2

V , INPUT SIGNAL VOLTAGE (V)

-6

-4

-2

= 5V

= 0V

= -5V

T = 25 C

R = 100k , R = 10k

Ω

100

Ω

500

Ω

Figure 9-2. ON Characteristics for 1 of 8 Channels (CD4051B)

9.3 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the

Electrical Characteristics.

Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a

single supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled VCC, then a 0.01-μF

or 0.022-μF capacitor is recommended for each VCC because the VCC pins will be tied together internally.

For devices with dual supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass

capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject

different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor

should be installed as close to the power terminal as possible for best results.

9.4 Layout

9.4.1 Layout Guidelines

Reflections and matching are closely related to loop antenna theory, but different enough to warrant their

own discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This reflection is

primarily due to the change of width of the trace. At the apex of the turn, the trace width is increased to 1.414

times its width. This upsets the transmission line characteristics, especially the distributed capacitance and

self–inductance of the trace — resulting in the reflection. It is a given that not all PCB traces can be straight, and

so they will have to turn corners. Figure 9-3 shows progressively better techniques of rounding corners. Only the

last example maintains constant trace width and minimizes reflections.

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CD4051B, CD4052B, CD4053B

SCHS047K – AUGUST 1998 – REVISED MARCH 2023

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