CD4052BM datasheet(22/48 Pages) TI

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INH

COMMON

OUT/IN

16 V

IN/OUT

BINARY TO

1 OF 2

DECODERS

WITH

INHIBIT

LOGIC

LEVEL

CONVERSION

VDD

COMMON

OUT/IN

COMMON

OUT/IN

ax OR ay

bx OR by

cx OR cy

All inputs are protected by standard CMOS protection network.

Figure 8-3. Functional Block Diagram, CD4053B

8.3 Feature Description

The CD405xB line of multiplexers and demultiplexers can accept a wide range of digital and analog signal levels.

Digital signals range from 3 V to 20 V, and analog signals are accepted at levels ≤ 20 V. The devices have low

ON resistance, typically 125 Ω over 15 VP-P signal input range for VDD – VEE = 18 V. This feature allows for very

little signal loss through the switch. Matched switch characteristics are typically rON = 5 Ω for VDD – VEE = 15 V.

The CD405xB devices also have high OFF resistance, which keeps from wasting power when the switch is

in the OFF position, with typical channel leakage of ±100 pA at VDD – VEE = 18 V. Very low quiescent power

dissipation under all digital-control input and supply conditions, typically 0.2 µW at VDD – VSS = VDD – VEE = 10

V keeps power consumption total very low. All devices have been 100% tested for quiescent current at 20 V with

maximum input current of 1 µA at 18 V over the full package temperature range, and only 100 nA at 18 V and

25°C.

Logic-level conversion for digital addressing signals of 3 V to 20 V (VDD – VSS = 3 V to 20 V) to switch analog

signals to 20 VP-P (VDD – VEE = 20 V). Binary address decoding on chip makes channel selection easy. When

channels are changed, a break-before-make system eliminates channel overlap.

CD4051B, CD4052B, CD4053B

SCHS047K – AUGUST 1998 – REVISED MARCH 2023

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