STR91XF datasheet(22/72 Pages) STMICROELECTRONICS

22 / 72 page

Functional overview

STR91xF

22/72

Figure 3.

JTAG chaining inside the STR91xF

2.15.1 In-system-programming

The JTAG interface is used to program or erase all memory areas of the STR91xF device. The

pin RESET_INn must be asserted during ISP to prevent the CPU from fetching invalid

instructions while the Flash memories are being programmed.

Note that the 32 bytes of OTP memory locations cannot be erased by any means once

programmed by JTAG ISP or the CPU.

2.15.2 Boundary scan

Standard JTAG boundary scan testing compliant with IEEE-1149.1 is available on the majority

of pins of the STR91xF for circuit board test during manufacture of the end product. STR91xF

pins that are not serviced by boundary scan are the following:

●

JTAG pins JTCK, JTMS, JTDI, JTDO, JTRSTn, JRTCK

●

Oscillator input pins X1_CPU, X2_CPU, X1_RTC, X2_RTC

●

Tamper detect input pin TAMPER_IN (128-pin package only)

2.15.3 CPU debug

The ARM966E-S CPU core has standard ARM EmbeddedICE-RT logic, allowing the STR91xF

to be debugged through the JTAG interface. This provides advanced debugging features

making it easier to develop application firmware, operating systems, and the hardware itself.

JTDI

JTMS

JTCK

JTDO

TDI

TMS

TCK

TDO

TMS TCK

TDI

JTAG TAP CONTROLLER #1

JTAG TAP CONTROLLER #3

BURST FLASH

MEMORY DIE

ARM966ES DIE

BOUNDARY SCAN

STR91xx

JTRSTn

TRST

TDI

TMS

TCK

TDO

JTAG TAP CONTROLLER #2

CPU DEBUG

TRST

JRTCK

TRST

MAIN FLASH

SECONDARY FLASH

JTAG

Instruction

5 bits for TAP #1

4 bits for TAP #2

JTAG

Instruction

is 8 bits

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