STR91XF datasheet(15/72 Pages) STMICROELECTRONICS

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STR91xF

Functional overview

15/72

Figure 2.

Clock control

2.10.2 Reference clock (RCLK)

The main clock (fMSTR) can be divided to operate at a slower frequency reference clock (RCLK)

for the ARM core and all the peripherals. The RCLK provides the divided clock for the ARM

core, and feeds the dividers for the AHB, APB, External Memory Interface, and FMI units.

2.10.3 AHB clock (HCLK)

The RCLK can be divided by 1, 2 or 4 to generate the AHB clock. The AHB clock is the bus

clock for the AHB bus and all bus transfers are synchronized to this clock. The maximum HCLK

frequency is 96MHz.

2.10.4 APB clock (PCLK)

The RCLK can be divided by 1, 2, 4 or 8 to generate the APB clock. The APB clock is the bus

clock for the APB bus and all bus transfers are synchronized to this clock. Many of the

peripherals that are connected to the AHB bus also use the PCLK as the source for external

bus data transfers. The maximum PCLK frequency is 48MHz.

2.10.5 Flash memory interface clock (FMICLK)

The FMICLK clock is an internal clock derived from RCLK, defaulting to RCLK frequency at

power up. The clock can be optionally divided by 2. The FMICLK determines the bus bandwidth

between the ARM core and the Flash memory. Typically, codes in the Flash memory can be

fetched one word per FMICLK clock in burst mode. The maximum FMICLK frequency is

96MHz.

2.10.6 Baud rate clock (BRCLK)

The baud rate clock is an internal clock derived from fMSTR that is used by the three on-chip

UART peripherals for baudrate generation. The frequency can be optionally divided by 2.

MII_PHYCLK

25MHz

PHYSEL

X1_CPU

X1_RTC

X2_RTC

EXTCLK_TOT1

EXTCLK_T2T3

USB_CLK48M

4-25MHz

48MHz

Main

OSC

RTC

OSC

16-bit prescaler

fOSC

PLL

32.768kHz

fRTC

TIM01CLK

TIM23CLK

fPLL

fMSTR

Master CLK

1/2

RCLK

DIV

(1,2,4,8,16,1024)

BRCLK

To UART

USBCLK

To USB

RCLK

AHB DIV

(1,2,4)

APB DIV)

(1,2,4,8)

1/2

HCLK

PCLK

FMICLK

CPUCLK

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