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NAND04GW3B2B bảng dữ liệu(PDF) 45 Page - STMicroelectronics

tên linh kiện NAND04GW3B2B
Giải thích chi tiết về linh kiện  4 Gbit, 8 Gbit, 2112 Byte/1056 Word Page 3V, NAND Flash Memories
PDF  58 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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NAND04GW3B2B bảng dữ liệu(HTML) 45 Page - STMicroelectronics

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NAND04GW3B2B, NAND08GW3B2A
DC and AC parameters
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tDZRL
tIR
Data Hi-Z to Read Enable Low
Min
0
ns
tEHQZ
tCHZ
Chip Enable High to Output Hi-Z
Max
50
ns
tRHQZ
tRHZ
Read Enable High to Output Hi-z
Max
50
ns
tELQV
tCEA
Chip Enable Low to Output Valid
Max
30
ns
tRHRL1
tREH
Read Enable High to
Read Enable Low
Read Enable High Hold time
Min
10
ns
tEHQX
tCOH
Chip Enable high to Output Hold
Min
15
ns
tRLRH
tRP
Read Enable Low to
Read Enable High
Read Enable Pulse Width
Min
15
ns
tRLRL
tRC
Read Enable Low to
Read Enable Low
Read Cycle time
Min
30
ns
tRLQV
tREA
Read Enable Low to
Output Valid
Read Enable Access time
Max
25
ns
Read ES Access time(2)
tWHBH
tR
Write Enable High to
Ready/Busy High
Read Busy time
Max
25
µs
tWHBL
tWB
Write Enable High to Ready/Busy Low
Max
100
ns
tWHRL
tWHR
Write Enable High to Read Enable Low
Min
60
ns
tRHRL2
tCRRH
Read Enable High hold time during Cache Read operation
Min
100
ns
tWHWH
tADL
(3)
Last Address latched to Data Loading Time during Program
operations
Min
100
ns
tVHWH
tVLWH
tWW
(4)
Write Protection time
Min
100
ns
1.
The time to Ready depends on the value of the pull-up resistor tied to the Ready/Busy pin. See Figure 33, Figure 34 and
Figure 35.
2.
ES = Electronic Signature.
3.
tADL is the time from W rising edge during the final address cycle to W rising edge during the first data cycle.
4.
During a Program/Erase Enable Operation, tWW is the delay from WP high to W High.
During a Program/Erase Disable Operation, tWW is the delay from WP Low to W High.
Table 21.
AC Characteristics for Operations(1) (continued)



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