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NAND04GW3B2B bảng dữ liệu(PDF) 44 Page - STMicroelectronics

tên linh kiện NAND04GW3B2B
Giải thích chi tiết về linh kiện  4 Gbit, 8 Gbit, 2112 Byte/1056 Word Page 3V, NAND Flash Memories
PDF  58 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

NAND04GW3B2B bảng dữ liệu(HTML) 44 Page - STMicroelectronics

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DC and AC parameters
NAND04GW3B2B, NAND08GW3B2A
44/58
Table 20.
AC Characteristics for Command, Address, Data Input
Symbol
Alt.
Symbol
Parameter
NAND04GW3B2B,
NAND08GW3B2A
Unit
tALLWH
tALS
Address Latch Low to Write Enable high
AL Setup time
Min
15
ns
tALHWH
Address Latch High to Write Enable high
tCLHWH
tCLS
Command Latch High to Write Enable high
CL Setup time
Min
15
ns
tCLLWH
Command Latch Low to Write Enable high
tDVWH
tDS
Data Valid to Write Enable High
Data Setup
time
Min
15
ns
tELWH
tCS
Chip Enable Low to Write Enable high
E Setup time
Min
25
ns
tWHALH
tALH
Write Enable High to Address Latch High
AL Hold time
Min
5
ns
tWHCLH
tCLH
Write Enable High to Command Latch High
CL hold time
Min
5
ns
tWHCLL
Write Enable High to Command Latch Low
tWHDX
tDH
Write Enable High to Data Transition
Data Hold
time
Min
5
ns
tWHEH
tCH
Write Enable High to Chip Enable High
E Hold time
Min
5
ns
tWHWL
tWH
Write Enable High to Write Enable Low
W High Hold
time
Min
10
ns
tWLWH
tWP
Write Enable Low to Write Enable High
W Pulse
Width
Min
20
ns
tWLWL
tWC
Write Enable Low to Write Enable Low
Write Cycle
time
Min
35
ns
Table 21.
AC Characteristics for Operations(1)
Symbol
Alt.
Symbol
Parameter
NAND04GW3B2B,
NAND08GW3B2A
Unit
tALLRL1
tAR
Address Latch Low to
Read Enable Low
Read Electronic Signature
Min
15
ns
tALLRL2
Read cycle
Min
15
ns
tBHRL
tRR
Ready/Busy High to Read Enable Low
Min
20
ns
tBLBH1
Ready/Busy Low to
Ready/Busy High
Read Busy time
Max
25
µs
tBLBH2
tPROG
Program Busy time
Max
700
µs
tBLBH3
tBERS
Erase Busy time
Max
3
ms
tBLBH4
Reset Busy time, during ready
Max
5
µs
tBLBH5
tCBSY
Cache Busy time
Typ
3
µs
Max
700
µs
tWHBH1
tRST
Write Enable High to
Ready/Busy High
Reset Busy time, during read
Max
5
µs
Reset Busy time, during program
Max
10
µs
Reset Busy time, during erase
Max
500
µs
tCLLRL
tCLR
Command Latch Low to Read Enable Low
Min
15
ns



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