NAND04GW3B2B datasheet(21/58 Pages) STMICROELECTRONICS

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NAND04GW3B2B, NAND08GW3B2A

Device operations

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6.2

Cache Read

The Cache Read operation is used to improve the read throughput by reading data using

the Cache Register. As soon as the user starts to read one page, the device automatically

loads the next page into the Cache Register.

An Cache Read operation consists of three steps (see Table 7: Commands):

One bus cycle is required to setup the Cache Read command (the same as the

standard Read command).

Five (refer to Table 5: Address Insertion) bus cycles are then required to input the Start

Address.

One bus cycle is required to issue the Cache Read confirm command to start the P/E/R

Controller.

The Start Address must be at the beginning of a page (Column Address = 00h, see Table 6:

Address Definition). This allows the data to be output uninterrupted after the latency time

(tBLBH1), see Figure 7: Cache Read Operation.

The Ready/Busy signal can be used to monitor the start of the operation. During the latency

period the Ready/Busy signal goes Low, after this the Ready/Busy signal goes High, even if

the device is internally downloading page n+1.

Once the Cache Read operation has started, the Status Register can be read using the

Read Status Register command.

During the operation, SR5 can be read, to find out whether the internal reading is ongoing

(SR5 = ‘0’), or has completed (SR5 = ‘1’), while SR6 indicates whether the Cache Register

is ready to download new data.

To exit the Cache Read operation an Exit Cache Read command must be issued (see

Table 7: Commands).

If the Exit Cache Read command is issued while the device is internally reading page n+1,

page n will still be output, but not page n+1.

Figure 7.

Cache Read Operation

I/O

Address

Inputs

ai8661c

00h

Read

Setup

Code

31h

Cache

Read

Confirm

Code

Busy

tBLBH1

(Read Busy time)

1st page

Data Output

2nd page

3rd page

last page

34h

Exit

Cache

Read

Code

Block N

tBLBH4

tRHRL2

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