PIC18F6310ESLASHPTSQTP datasheet(98/404 Pages) MICROCHIP

98 / 404 page

PIC18F6310/6410/8310/8410

DS39635A-page 96

Preliminary

 2004 Microchip Technology Inc.

7.3

8-Bit Mode

The

external

memory

interface

implemented

PIC18F6410 devices operates only in Multiplexed 8-bit

mode; data shares the 8 Least Significant bits of the

address bus.

Figure 7-1 shows an example of 8-bit Multiplexed

mode for PIC18F8310/8410 devices. This mode is

used for a single 8-bit memory connected for 16-bit

operation. The instructions will be fetched as two 8-bit

bytes on a shared data/address bus. The two bytes are

sequentially fetched within one instruction cycle (TCY).

Therefore, the designer must choose external memory

devices according to timing calculations based on 1/2

TCY (2 times the instruction rate). For proper memory

speed selection, glue logic propagation delay times

must be considered along with setup and hold times.

The Address Latch Enable (ALE) pin indicates that the

address bits A<15:0> are available on the external

memory interface bus. The Output Enable signal (OE)

will enable one byte of program memory for a portion of

the instruction cycle, then BA0 will change and the

second byte will be enabled to form the 16-bit instruc-

tion word. The Least Significant bit of the address, BA0,

must be connected to the memory devices in this

mode. The Chip Enable signal (CE) is active at any

time

that

the

microcontroller

accesses

external

memory, whether reading or writing; it is inactive

(asserted high) whenever the device is in Sleep mode.

This generally includes basic EPROM and Flash devices.

It allows table writes to byte-wide external memories.

During a TBLWT instruction cycle, the TABLAT data is

presented on the upper and lower bytes of the

AD15:AD0 bus. The appropriate level of the BA0

control line is strobed on the LSb of the TBLPTR.

FIGURE 7-7:

8-BIT MULTIPLEXED MODE EXAMPLE

AD<7:0>

A<19:16>

ALE

D<15:8>

373

A<19:0>

A<x:1>

D<7:0>

WR(1)

Note

This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.

WRL

D<7:0>

PIC18F8410

AD<15:8>

Address Bus

Data Bus

Control Lines

BA0

PIC18F6310E/PTSQTP bảng dữ liệu(PDF) 98 Page - Microchip Technology

PIC18F6310E/PTSQTP bảng dữ liệu(HTML) 98 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL