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MCF5373CAB180 bảng dữ liệu(PDF) 32 Page - Freescale Semiconductor, Inc

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Giải thích chi tiết về linh kiện  Microprocessor Data Sheet
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MCF5373CAB180 bảng dữ liệu(HTML) 32 Page - Freescale Semiconductor, Inc

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MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Preliminary
Preliminary Electrical Characteristics
Freescale Semiconductor
32
5.13 I2C Input/Output Timing Specifications
Table 16 lists specifications for the I2C input timing parameters shown in Figure 21.
Table 17 lists specifications for the I2C output timing parameters shown in Figure 21.
S4
SSI_BCK rising edge to SSI_MCLK edge
10
—
ns
S5
SSI_MCLK edge to SSI_BCLK rising edge
10
—
ns
S6
SSI_TXD/SSI_RXD data set-up time
10
—
ns
S7
SSI_TXD/SSI_RXD data hold time
10
—
ns
NOTES:
1fs is the sampling frequency. SSI_BCLK can be operated upto 512 times the sampling frequency to a max frequency of 49.152MHz
Table 16. I2C Input Timing Specifications between SCL and SDA
Num
Characteristic
Min
Max
Units
I1
Start condition hold time
2
—
tcyc
I2
Clock low period
8
—
tcyc
I3
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH =2.4 V)
—
1
ms
I4
Data hold time
0
—
ns
I5
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL =0.5 V)
—
1
ms
I6
Clock high time
4
—
tcyc
I7
Data setup time
0
—
ns
I8
Start condition setup time (for repeated start condition only)
2
—
tcyc
I9
Stop condition setup time
2
—
tcyc
Table 17. I2C Output Timing Specifications between SCL and SDA
Num
Characteristic
Min
Max
Units
I11
Start condition hold time
6
—
tcyc
I2 1
Clock low period
10
—
tcyc
I3 2
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH =2.4 V)
—
—
µs
I4 1
Data hold time
7
—
tcyc
I5 3
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
3
ns
I6 1
Clock high time
10
—
tcyc
I7 1
Data setup time
2
—
tcyc
I8 1
Start condition setup time (for repeated start condition only)
20
—
tcyc
I9 1
Stop condition setup time
10
—
tcyc
Table 15. SSI Timing (continued)
Num
Description
1.8 +/- 0.10V
Unit
Minimum
Maximum



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