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ICS9LRS3187B bảng dữ liệu(PDF) 7 Page - Renesas Technology Corp |
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ICS9LRS3187B bảng dữ liệu(HTML) 7 Page - Renesas Technology Corp |
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7 / 21 page ![]() IDT® Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems 7 Datasheet Byte 0 FS Readback and PLL Selection Register Bit Pin Name Description Type 0 1 Default 7 - FSLC CPU Freq. Sel. Bit R Latch 6 - Reserved Reserved RW - - 0 5 - Reserved Reserved RW - - 1 4 - iAMT_EN Set via SMBus RW (Sticky "1") Legacy Mode iAMT Enabled 0 3 Reserved Reserved RW 0 2 - Reserved Reserved RW 0 1 - SATA_SEL Select source for SATA clock RW SATA (SRC2 100MHz_SS) = SRC_Main SATA (100MHz non_SS) = SATA PLL 0 0- PD_Restore 1 = on Power Down de-assert return to last known state 0 = clear all SMBus configurations as if cold power- on and go to latches open state This bit is ignored and treated at '1' if device is in iAMT mode. RW Configuration Not Saved Configuration Saved 1 Byte 1 DOT96 Select and PLL3 Quick Config Register, Bit Pin Name Description Type 0 1 Default 7 Reserved Reserved RW - - 1 6 SRC_PLL_SSC_SEL Select 0.5% down or center SSC RW Down spread Center spread 0 5 Reserved Reserved RW - - 1 4 Reserved Reserved RW 0 3 27SS PLL CF2 27SS PLL Quick Config Bit 2 RW 0 2 27SS PLL _CF1 27SS PLL Quick Config Bit 1 RW 1 1 27SS PLL CF0 27SS PLL Quick Config Bit 0 RW 0 0 Reserved Reserved RW - - 1 Byte 2 Output Enable Register Bit Pin Name Description Type 0 1 Default 7 REF_3L_OE Output enable for REF0, if disabled output is tri- stated RW Output Disabled Output Enabled 1 6 Reserved Reserved RW - - 1 5 Reserved Reserved RW - - 1 4 Reserved Reserved RW - - 1 3 Reserved Reserved RW - - 1 2 Reserved Reserved RW - - 1 1 Reserved Reserved RW - - 1 0 Reserved Reserved RW - - 1 Byte 3 Output Enable Register Bit Pin Name Description Type 0 1 Default 7 Reserved Reserved RW - - 1 6 Reserved Reserved RW - - 1 5 Reserved Reserved RW - - 1 4 Reserved Reserved RW - - 1 3 Reserved Reserved RW - - 1 2 Reserved Reserved RW - - 1 1 Reserved Reserved RW 1 0 Reserved Reserved RW - - 1 See Table 2: pin 6/7 Configuration |
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