IDT® Programmable Timing Control Hub for Intel Based Systems

1602F—11/04/11

ICS9LRS3187B

Programmable Timing Control Hub for Intel Based Systems

4

Datasheet

Table 1: CPU Frequency Select Table

FSLC

B0b7

CPU

MHz

SRC

MHz

REF

MHz

DOT

MHz

0 (Default)

133.33

1

100.00

1. FS

LC is a low-threshold input.Please see VIL_FS and VIH_FS specifications in

the Input/Supply/Common Output Parameters Table for correct values.

Also refer to the Test Clarification Table.

100.00

14.318

96.00

Table 2: pin 6, 7 Configuration

Pin 6

Pin 7

Spread

MHz

MHz

%

00

0

27MHz_nonSS

27MHz_SS

-1.75%

00

1

27MHz_nonSS

27MHz_SS

+-0.5%

01

0

27MHz_nonSS

27MHz_SS

-0.5%

Default

01

1

27MHz_nonSS

27MHz_SS

-1%

10

0

27MHz_nonSS

27MHz_SS

-1.5%

10

1

27MHz_nonSS

27MHz_SS

-2%

11

0

27MHz_nonSS

27MHz_SS

-0.75%

11

1

27MHz_nonSS

27MHz_SS

-1.25%

B1b3

B1b2

B1b1

Comment

Table 3: IO_Vout select table

B9b2

B9b1

B9b0

IO_Vout

00

0

0.3V

00

1

0.4V

01

0

0.5V

01

1

0.6V

10

0

0.7V

10

1

0.8V

11

0

0.9V

11

1

1.0V