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HC705C9AGRS/D bảng dữ liệu(PDF) 109 Page - NXP Semiconductors

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Giải thích chi tiết về linh kiện  General Release Specification
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General Release Specification
SPI Registers
MC68HC705C9A — Rev. 2.0
Serial Peripheral Interface
10.6.3 Serial Peripheral Data I/O Register (SPDR)
The serial peripheral data I/O register, shown in Figure 10-6, is used to
transmit and receive data on the serial bus. Only a write to this register
will initiate transmission/reception of another byte and this will only occur
in the master device. At the completion of transmitting a byte of data, the
SPIF status bit is set in both the master and slave devices.
When the user reads the serial peripheral data I/O register, a buffer is
actually being read. The first SPIF must be cleared by the time a second
transfer of the data from the shift register to the read buffer is initiated or
an overrun condition will exist. In cases of overrun, the byte which
causes the overrun is lost.
A write to the serial peripheral data I/O register is not buffered and
places data directly into the shift register for transmission.
$000C
Bit 7
654321
Bit 0
Read:
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
Write:
Reset:
UUUUUUUU
U = Undetermined
Figure 10-6. PI Data Register (SPDR)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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