HC705C9AGRSSLASHD datasheet(106/157 Pages) NXP

106 / 157 page

General Release Speciﬁcation

SPI Registers

MC68HC705C9A — Rev. 2.0

Serial Peripheral Interface

DWOM — Port D Wire-OR Mode Option

This read/write bit disables the high side driver transistors on port D

outputs so that port D outputs become open-drain drivers. DWOM

affects all seven port D pins together. This option is only available

when configured as a C9A.

1 = Port D outputs act as open-drain outputs.

0 = Port D outputs are normal CMOS outputs.

MSTR — Master Mode Select

This read/write bit selects master mode operation or slave mode

operation. Reset clears the MSTR bit.

1 = Master mode

0 = Slave mode

CPOL — Clock Polarity

When the clock polarity bit is cleared and data is not being

transferred, a steady state low value is produced at the SCK pin of the

master device. Conversely, if this bit is set, the SCK pin will idle high.

This bit is also used in conjunction with the clock phase control bit to

produce the desired clock-data relationship between master and

slave. See Figure 10-1.

CPHA — Clock Phase

The clock phase bit, in conjunction with the CPOL bit, controls the

clock-data relationship between master and slave. The CPOL bit can

be thought of as simply inserting an inverter in series with the SCK

line. The CPHA bit selects one of two fundamentally different clocking

protocols. When CPHA = 0, the shift clock is the OR of SCK with SS.

As soon as SS goes low, the transaction begins and the first edge on

SCK invokes the first data sample. When CPHA=1, the SS pin may

be thought of as a simple output enable control. See Figure 10-1.

SPR1 and SPR0 — SPI Clock Rate Selects

These read/write bits select one of four master mode serial clock

rates, as shown in Table 10-1. They have no effect in the slave mode.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705C9AGRS/D bảng dữ liệu(PDF) 106 Page - NXP Semiconductors