ZAMC4100 datasheet(15/156 Pages) RENESAS

15 / 156 page

ZAMC4100 Datasheet

January 26, 2016

Table 1.3

ESD Protection

Test Method

Test Setup Standard

Guaranteed ESD/Latch-up

Robustness on IC Level

HBM (Human Body Model)

MIL 883C, Method 3015.7

or EIA/JESD22A114-A

± 2kV (all pins) with 100pF and 1.5kΩ

CDM (Charged Device Model)

AEC – Q100 – 011 Rev. B

± 500V (all pins)

System Level (Human Body Discharge)

IEC 61000-4-2

± 6kV for LIN

(1) and VBAT(2)

Latch-up

EIA/JESD78A

100mA@25˚C

(1) External circuitry is required for meeting the system-level ESD specification for the LIN interface.

(2) VBAT is the common supply terminal on the application PCB where all ZAMC4100 supply pins are connected.

1.2.

Electrical Parameters

Note: Parameters are specified for junction temperature range -40°C to 125°C unless otherwise stated.

1.2.1.

Supply and Supply Monitoring

Table 1.4

Supply Voltages and Currents

Parameter

Symbol

Min.

Typ.

Max.

Unit

Supply Voltage Range (voltage drop in external circuitry not included)

Nominal operating voltage

VSUP

LIN operating voltage

VSUP_LIN

Supply Current Range

NORMAL Mode

IRUN

STANDBY Mode

ISTBY

SLEEP Mode (measured at TJ=27°C; VSUP=13V through all VSS pins)

ISLEEP

µA

Switchable Analog Supply Voltage (to S_P pin)

Voltage range (S_P pin unloaded)

VSP

4.5

5.5

Voltage range (S_P pin loaded with 5mA)

VSP_5mA

3.8

4.5

5.2

Nominal output current

ISP

Current limitation in case of short to GND

ISP_OC

GPIO Supply Voltage

Voltage range

VGPIO

2.97

3.3

3.63

ZAMC4100 bảng dữ liệu(PDF) 15 Page - Renesas Technology Corp

ZAMC4100 bảng dữ liệu(HTML) 15 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL