ZAMC4100 datasheet(42/156 Pages) RENESAS

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ZAMC4100 Datasheet

January 26, 2016

Table 3.9). In order to clear the SEIF flag, the MCU should clear the OVIF and UVIF flags.

In order to prevent false over-voltage or under-voltage events being flagged (caused by supply spikes), the OV

and UV interrupt signals are passed through a de-bounce circuit that filters out all events shorter than 20µs.

If the over-voltage or under-voltage event still exists, the OVIF and UVIF flags remain high even if the MCU is

attempting to clear them.

If the SEIFAC bit of register SMDCTRL (Table 3.5) is set high, the OVIF and UVIF flags are automatically cleared

when the over-voltage or under-voltage event is corrected and the supply remains stable for more than 20µs.

3.4.2.

ZAMC4100 Operation during Over-Voltage

During an over-voltage event, the SBC and MCU are fully functional. By default, the over-voltage event

automatically disables all drivers in order to prevent load damage. The MCU can re-enable the drivers by clearing

the OVIF flag. If this protection is not needed, it can be disabled by clearing the OVDP bit of the SMDCTRL

3.4.3.

ZAMC4100 Operation during Under-Voltage

When an under-voltage event occurs, the MCU chip is still fully functional. The SBC analog circuitry is

operational, but its supply is out of range; therefore the analog parameters cannot be guaranteed.

During an under-voltage event, the internal charge pump voltage is out of range, and proper driver operation is

not guaranteed. By default the under-voltage event automatically disables all drivers. The MCU can re-enable the

drivers by clearing the UVIF flag in the RSTSTAT register (Table 3.1).

Important note: The under-voltage driver protection can be disabled by clearing the UVDP bit in the SMDCTRL

the regular application.

3.4.4.

Charge Pump Voltage Monitoring

ZAMC4100 has internal circuitry for charge pump (CP) voltage monitoring, which is continually enabled during

system operation. If the charge pump voltage is out of range, an interrupt is generated and the drivers are

disabled. In order to prevent a false “charge pump voltage error” event flag (caused by supply spikes), the CP

interrupt signal passes through de-bounce circuitry that filters out all events shorter than 20µs.

A charge pump voltage error interrupt is indicated by the CPVEIF flag in the RSTSTAT register (Table 3.1). If

CPVEIF = HIGH, i.e. the CP voltage is out of range, all drivers are automatically disabled regardless of the value

of the driver enable bits.

The MCU can clear the interrupt by writing ‘1’ in the CPVEIF flag, but only if the CP voltage has recovered to its

valid range. If the CPVEIFAC bit of the SMDCTRL register (Table 3.5) is set high, then the CPVEIF flag is

automatically cleared when the CP voltage recovers to its valid range and remains valid for more than 20µs.

The CP voltage needs a settling time specified in Table 1.17 by parameter tCP_STL. Because tCP_STL is greater than

the power-up timer delay (tPWRT), after POR and wake-up from SLEEP, the CPVEIF flag will be set HIGH. If

CPVEIF auto-clear is enabled, the flag will be automatically cleared when time tCP_STL has expired, i.e. the CP

voltage has reached its valid range.

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