X80120, X80121

FN8151 Rev 0.00

Page 12 of 17

January 20, 2005

Bus Interface Information

Interface Conventions

The device supports a bidirectional bus oriented protocol. The

protocol defines any device that sends data onto the bus as a

transmitter, and the receiving device as the receiver. The

device controlling the transfer is called the master and the

device being controlled is called the slave. The master always

initiates data transfers, and provides the clock for both transmit

and receive operations. Therefore, the devices in this family

operate as slaves in all applications.

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read operation,

the master must either issue a STOP condition during the ninth

cycle or hold SDA HIGH during the ninth clock cycle and then

issue a STOP condition.

Serial Clock and Data

Data states on the SDA line can change only during SCL LOW.

SDA state changes during SCL HIGH are reserved for

indicating START and STOP conditions (See Figure 11).

Serial Start Condition

All commands are preceded by the START condition, which is

a HIGH to LOW transition of SDA when SCL is HIGH. The

device continuously monitors the SDA and SCL lines for the

START condition and does not respond to any command until

this condition has been met. On power up, the SCL pin must

be brought LOW prior to the START condition.

Serial Stop Condition

All communications must be terminated by a STOP condition,

which is a LOW to HIGH transition of SDA when SCL is HIGH,

followed by a HIGH to LOW on SCL. After going LOW, SCL

TABLE 4. REGISTER ADDRESS MAP

BYTE

ADDR.

NAME

CONTROI/STATUS

BIT

MEMORY

TYPE

7

654

321

0

00H

CR0

Write Enable

WEL

0

0

0

0

0

0

0

Volatile

01H

CR1

EEPROM Block

Control

WPEN

0

0

BP1

BP0

0

0

0

EEPROM

02H

CR2

POR Timing

0

0

0

0

TPOR1

TPOR0

0

0

EEPROM

03H

CR3

ViGDO TIme Delay

T4D1

T4D0

0

0

0

0

T1D1

T1D0

EEPROM

FF

FDR

Fault Detection

Register

0

0

0

0

V40S

0

0

V10S

Volatile

TABLE 5. HARDWARE/SOFTWARE CONTROL AND FAULT DETECTION BITS SUMMARY

OPERATION

CONTROL/

STATUS

LOCATION(S)

DESCRIPTION (SEE FUNCTIONAL FOR DETAILS)

REGISTER

BITS

SOFTWARE CONTROL BITS

EEPROM Write Enable

WEL

CR0

7

WEL = 1 enables write operations to the control registers and EEPROM.

WEL = 0 prevents write operations.

EEPROM Write Protect

WPEN

CR1

7

WPEN = 1 (and WP pin HIGH) prevents writes to the control registers and

the EEPROM.

EEPROM Block Protect

BP1

BP0

CR1

4:3

BP1=0, BP0=0 : No EEPROM memory protected.

BP1=0, BP0=1 : Upper 1/4 of EEPROM memory protected

BP1=1, BP0=0 : Upper 1/2 of EEPROM memory protected.

BP1=1, BP0=1 : All of EEPROM memory protected.

RESET Time Delay

TPOR0

TPOR1

CR2

3:2

TPOR1=0, TPOR0=0 : RESET delay = 100ms

TPOR1=0, TPOR0=1 : RESET delay = 500ms

TPOR1=1, TPOR0=0 : RESET delay = 1s

TPOR1=1, TPOR0=1 : RESET delay = 5s

V1GDO Time Delay

T1D0

T1D1

CR3

1:0

TiD1=0, TiD0=0 : ViGDO delay = 100ms

TiD1=0, TiD0=1 : ViGDO delay = 500ms

TiD1=1, TiD0=0 : ViGDO delay = 1s

TiD1=1, TiD0=1 : ViGDO delay = 5s

V4GDO Time Delay

T4D0

T4D1

CR3

7:6

STATUS BITS

1st Voltage Monitor

V1OS

FDR

0

V1OS = 0 : V1GDO pin has been asserted (must be preset to 1).

4th Voltage Monitor

V4OS

FDR

3

V4OS = 0 : V4GDO pin has been asserted (must be preset to 1).