X80120, X80121

FN8151 Rev 0.00

Page 9 of 17

January 20, 2005

Manual Reset

The manual reset option allows a hardware reset of the power

sequencing pins. These can be used to recover the system in

the event of an abnormal operating condition. Activating the

MR pin for more than 5

s sets all of the ViGDO outputs and the

RESET output active (LOW). When MR is released (and if all

supplies are still at their proper operating voltage) then the

ViGDO and RESET pins will be released after their

programmed delay periods.

Dual Voltage Monitoring

X80120 monitors 2 voltage inputs. When the V1MON or

V4MON input is detected to be above the input threshold, the

respective output (V1GDO or V4GDO) goes inactive (LOW).

The ViGDO signal is de-asserted after a delay of 100ms. This

delay can be changed on each ViGDO output individually with

bits in register CR3. The delay can be 100ms, 500ms, 1s and

5s. Each ViGDO signal remains active until its associated

ViMON input rises above the threshold.

Fault Detection

The X80120 contains a Fault Detection Register (FDR) that

provides the user the status of the causes for a RESET pin

active (See Table 20).

At power-up, the FDR is defaulted to all “0”. The system needs

to initialize the register to 09h before the actual monitoring can

take place. In the event that any one of the monitored sources

fail, the corresponding bit in the register changes from a “1” to

a “0” to indicate the failure. When a RESET is detected by the

main controller, the controller should read the FDR and note

the cause of the fault. After reading the register, the controller

can reset the register bit back to all “1” in preparation for future

failure conditions.

Flexible Power Sequencing of Multiple Power

Supplies

The X80120 provides several circuits such as multiple voltage

monitors, programmable delays, and output drive signals that

can be used to set up flexible power monitoring or sequencing

schemes system power supplies. Below are two examples:

1. Power Up of Supplies In Parallel Using Programmable

Delays. (See Figure 7 and Figure 8).

The X80120 monitors several power supplies, powered by

the same source voltage, that all begin power up at the

same time. Each voltage source is fed into the ViMON

inputs to the X80120. The ViMON inputs monitor the

voltage to make sure it has reached the minimum desired

level. When each voltage monitor determines that its input

is good, a counter starts. After the programmed delay time,

the X80120 sets the ViGDO signals LOW. The ViGDO

signals can be wire ORed together and tied to an interrupt

on the microcontroller. Any individual voltage failure can be

viewed in the Fault Detection Register.

In the factory default condition, each ViGDO output is

instructed to go LOW 100ms after the input voltage reaches

its threshold. However, each ViGDO delay is individually

selectable as 100ms, 500ms, 1s and 5s. The delay times

are charged via the SMBus during calibration of the system.

2. Power Up of Supplies Via Relay Sequencing Using Voltage

Monitors (see Figure 9 and Figure 10).

Several power supplies and their respective power up start

times can be controlled using the X80120 such that each of

the power supplies will start in a relay sequencing fashion.

In the following example, the 1st supply is allowed to power

up when the input regulated supply reaches an acceptable

threshold. Subsequent supplies power up after the prior

supply has reached its operating voltage. This configuration

ensures that each subsequent power supply turns on after

the preceding supplies voltage output is valid. Again, the

X80120 offers programmable delays for each voltage

monitor and this delay is selectable via the SMBus during

calibration of the system.

TABLE 2. ViGDO OUTPUT TIME DELAY OPTIONS

TiD1

TiD0

tDELAYi

0

0

100ms (default)

0

1

500ms

1

0

1 secs

1

1

5 secs

where i is the specific voltage monitor (i = 1, 4).

V4GDO

V4MON

V1GDO

V1MON

X80120/21

RESET

µC

VCC1

FPGA

VCC1

ASIC

VCC1

RESET

VCC2

MR

1.2V

3.3V

5V

Power

Supplies

IRQ

On/Off

On/Off

FIGURE 7. EXAMPLE APPLICATION OF PARALLEL POWER

CONTROL