X80120, X80121

FN8151 Rev 0.00

Page 6 of 17

January 20, 2005

Timing Diagrams

AC CHARACTERISTICS

fSCL

SCL Clock Frequency

400

kHz

tIN

Pulse width Suppression Time at

inputs

50

ns

tAA (Note 1) SCL LOW to SDA Data Out Valid

0.1

1.5

µs

tBUF

(Note 1)

Time the bus is free before start of new

transmission

1.3

µs

tLOW

Clock LOW Time

1.3

µs

tHIGH

Clock HIGH Time

0.6

µs

tSU:STA

Start Condition Setup Time

0.6

µs

tHD:STA

Start Condition Hold Time

0.6

µs

tSU:DAT

Data In Setup Time

100

ns

tHD:DAT

Data In Hold Time

0

µs

tSU:STO

Stop Condition Setup Time

0.6

µs

tDH (Note 1) Data Output Hold Time

50

ns

tR (Note 1) SDA and SCL Rise Time

20 +.1Cb

300

ns

tF (Note 1) SDA and SCL Fall Time

20 +.1Cb

300

ns

tSU:WP

WP Setup Time

0.6

µs

tHD:WP

WP Hold Time

0µs

tSU:ADR

A0, A1 Setup Time

0.6

µs

tHD:ADR

A0, A1 Hold Time

0

µs

tSU:VP

VP Setup Time

0.6

µs

Cb (Note 3) Capacitive load for each bus line

400

pF

tWC (Note 2) EEPROM Write Cycle Time

510

ms

NOTES:

1. This parameter is based on characterization data.

2. tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the

minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

3. This parameter is not 100% tested.

Serial Interface (Continued)Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tSU:STO

tHIGH

tSU:STA

tHD:STA

tHD:DAT

tSU:DAT

SCL

SDA IN

SDA OUT

tF

tLOW

tHD:DAT

tR

tDH

tAA

tBUF

tHD:STO

tBUF

FIGURE 4. BUS TIMING