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S12SCIV3/D bảng dữ liệu(PDF) 70 Page - NXP Semiconductors

tên linh kiện S12SCIV3/D
Giải thích chi tiết về linh kiện  The SoC Guide provides information about the MC9S12KG128 device made up of standard HCS12 blocks and the HCS12 processor core
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MC9S12KG128 SoC Guide — V01.01
Table A-13 3.3V ATD Conversion Performance
For the following definitions see also Figure A-1.
Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
Conditions are shown in Table A-4 unless otherwise noted
VREF = VRH - VRL = 3.328V. Resulting to one 8 bit count = 13mV and one 10 bit count = 3.25mV
fATDCLK = 2.0MHz
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
P 10-Bit Resolution
LSB
3.25
mV
2
P 10-Bit Differential Nonlinearity
DNL
–1.5
1.5
Counts
3
P 10-Bit Integral Nonlinearity
INL
–3.5
±1.5
3.5
Counts
4P 10-Bit Absolute Error1
NOTES:
1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
AE
-5
±2.5
5
Counts
5C 10-Bit Absolute Error at fATDCLK= 4MHz
AE
±7.0
Counts
6
P 8-Bit Resolution
LSB
13
mV
7
P 8-Bit Differential Nonlinearity
DNL
–0.5
0.5
Counts
8
P 8-Bit Integral Nonlinearity
INL
–1.5
±0.1
1.5
Counts
9P 8-Bit Absolute Error(1)
AE
-2.0
±1.5
2.0
Counts
DNL i
()
V
i
V
i1
–
–
1LSB
------------------------
1
–
=
INL n
()
DNL i
()
i1
=
n
∑
V
n
V
0
–
1LSB
--------------------
n
–
==
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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