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S12SCIV3/D bảng dữ liệu(PDF) 53 Page - NXP Semiconductors

tên linh kiện S12SCIV3/D
Giải thích chi tiết về linh kiện  The SoC Guide provides information about the MC9S12KG128 device made up of standard HCS12 blocks and the HCS12 processor core
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MC9S12KG128 SoC Guide — V01.01
and VDD2 are connected together internally. VSS1 and VSS2 are connected together internally. This
allows systems to employ better supply routing and further decoupling.
19.1.2 Recommended PCB Layout
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
•
Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins (C1 - C6).
•
Central point of the ground star should be the VSSR pin.
•
Use low ohmic low inductance connections between VSS1, VSS2 and VSSR.
•
VSSPLL must be directly connected to VSSR.
•
Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7,
C8 and Q1 as small as possible.
•
Do not place other signals or supplies underneath area occupied by C7, C8 and Q1 and the
connection area to the MCU.
•
Central power input should be fed in at the VDDA/VSSA pins.
Table 19-1 Recommended decoupling capacitor choice
Component
Purpose
Type
Value
C1
VDD1 filter cap
ceramic X7R
400nF
C2
VDD2 filter cap (80 QFP only)
ceramic X7R
400nF
C3
VDDA filter cap
ceramic X7R
100nF
C4
VDDR filter cap
X7R/tantalum
>=100nF
C5
VDDPLL filter cap
ceramic X7R
200nF
C6
VDDX filter cap
X7R/tantalum
>=100nF
C7
OSC load cap
C8
OSC load cap
C9
PLL loop filter cap
See PLL specification chapter
C10
PLL loop filter cap
R1
PLL loop filter res
Q1
Quartz
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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