DA9062 datasheet(63/101 Pages) RENESAS

63 / 101 page

DA9062

PMIC for Applications Requiring up to 8.5 A

Datasheet

Revision 3.8

15-Feb-2022

CFR0011-120-00

63 of 99

10.2 PCB Layout

1005

LX2

GND

VBUCK4

1005

GPIO0

GPIO1

VDDIO

VBUCK4

GPIO4

VBUCK3

VBUCK1

VBUCK2

GPIO2

GPIO3

VLDO1

VLDO2

VDD

LDO2

IREF

VREF

XIN

VSS

ANA

XOUT

VLDO3

VDD

LDO34

VBUCK3

1608

1005

2016

1608

LX1

Quiet ground

Figure 24: PCB Layout for DA9062

10.2.1

General Recommendations

Appropriate trace width and quantity of vias should be used for all power supply paths.

Too high trace resistances can prevent the system from achieving the best performance, for

example, the efficiency and the current ratings of switching converters might be degraded.

Furthermore, the PCB may be exposed to thermal hot spots, which can lead to critical overheating

due to the positive temperature coefficient of copper.

Special care must be taken with the DA9062 pad connections. The traces connecting the pads

should of the same width as the pads and they should become wider as soon as possible.

It is recommended to create a separate quiet ground to which the VREF capacitor, IREF resistor, and

the crystal capacitors are connected. The PCB layout should ensure these component grounds are

kept quiet, that is, they should be separated from the main ground return path for the noisy power

ground. The quiet ground can then be connected to the main ground at the paddle, as shown in

Figure 24.

All traces carrying high discontinuous currents should be kept as short as possible.

Noise sensitive analog signals, such as feedback lines or crystal connections, should be kept away

from traces carrying pulsed analog or digital signals. This can be achieved by separation or shielding

with quiet signals or ground traces.

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