DA9062 datasheet(42/101 Pages) RENESAS

42 / 101 page

DA9062

PMIC for Applications Requiring up to 8.5 A

Datasheet

Revision 3.8

15-Feb-2022

CFR0011-120-00

42 of 99

8.3.3.2

PWR_EN

PWR_EN (pin GPIO2) controls the POWER_EN bit and thereby the power mode of DA9062. It is

part of the power supply sequencer functionality described in Section 8.9. PWR_EN is an edge-

sensitive signal and its polarity can be chosen in the GPIO2_TYPE register. A wakeup event can be

generated after assertion of PWR_EN if so configured in GPIO2_WEN.

8.3.3.3

WDKICK

A rising edge of the WDKICK signal resets the watchdog counter. The polarity of the signal can be

chosen in the GPIO0_TYPE register. If the signal is kept asserted, the watchdog is disabled as the

counter is not incremented (WDG_MODE), see Section 8.15.

8.3.4

GPIO Forwarding

GPIO forwarding works between GPIOs 0, 1, 2, and 3. Any of these GPIs can be routed directly to

GPO0, 1, and 3 after debouncing. Forwarding is one of the options for the GPIO<x>_OUT register.

8.3.5

Analog Functions

GPIO0 and GPIO1 can be used as analog IOs. In this case, the normal GPIO functions are disabled.

The analog functions and their corresponding register bits are listed in Table 26.

Table 26: GPIO Analog Functions

GPIO

Analog Function

GPIO0

VDDQ

BUCK4_VTT_EN

GPIO1

VTTR

BUCK4_VTTR_EN

GPIO2

GPIO3

GPIO4

8.4

Dynamic Voltage Control

All of DA9062

’s buck converters can be controlled in several ways to achieve dynamic voltage

control (DVC). The buck converters feature a voltage ramping feature that enables smooth transition

from one voltage setting to another.

All output voltages can be controlled with software via the 2-wire interface (VBUCK<x>_A). The 2-

wire interface is operational when the device is in ACTIVE mode.

8.5

Regulator Voltage A and B Selection

In addition, all regulators feature A and B settings which can be programmed with different voltages

(VBUCK<x>_A, VBUCK<x>_B), one of which is chosen according to the operating mode of the

system (VBUCK<x>_SEL, VLDO<x>_SEL). In addition to the output voltage, the A and B settings

include a bit to force the regulator into SLEEP mode which reduces the quiescent current.

The selection between the A and B settings can be done either with software via the 2-wire interface

or by the power sequencer, see Section 8.9. Furthermore, each regulator can be enabled with a GPI

pin, see Section 8.3.1.1, and the selection between the A and B settings done with another GPI.

DA9062 bảng dữ liệu(PDF) 42 Page - Renesas Technology Corp

DA9062 bảng dữ liệu(HTML) 42 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL