10.2

Output capacitors

Output capacitor choice depends on the output voltage ripple and the output voltage deviation during a load

transient.

During steady-state conditions, the output voltage ripple is influenced by both ESR and capacitive value of the

output capacitors as follows:

ΔVOUT_ESR=ΔIL⋅ESR

(9)

ΔVOUT_C=ΔIL⋅ 1

8⋅COUT⋅FSW

(10)

Where ΔIL is the inductor current ripple. Since they are not in phase, the total ripple is lower than the sum of their

modules. Both ESL and board parasitic inductance can contribute to the output ripple significantly.

During a load variation, the output capacitors supply the load with the current or absorb the current in excess

delivered by the inductor until converter reaction is completed. In fact, even if the controller reacts immediately to

the load transient saturating the duty cycle to 80% or 0%, the current slew rate is limited by the inductance.

The output voltage drop, based on ESR and capacitive charge/discharge and considering an ideal load-step, can

be estimated as follows:

ΔVOUT_ESR=ΔIOUT⋅ESR

(11)

ΔVOUT_C= L⋅ΔIOUT2

2⋅COUT⋅ΔVL

(12)

Where ΔVL is the voltage applied to the inductor during the transient (VIN- VOUT for the load appliance or VOUT for

the load removal).

MLCC capacitors typically have low ESR to minimize the ripple but also have low capacitance which doesn’t

minimize the voltage deviation during the load transient. On contrary, electrolytic capacitors usually have higher

capacitance to minimize capacitive voltage deviation during the load transient, but also higher ESR value resulting

in higher ripple voltage and resistive voltage drop. For these reasons, a mix between the electrolytic and MLCC

capacitor is suggested so to minimize the ripple and reduce the voltage deviation in dynamic mode.

10.3

Input capacitors

The input capacitor bank is designed mainly to stand input RMS current, which depends on the output current

(IOUT) and duty cycle (D) for the regulation as follows:

IRMS=IOUT⋅ D⋅ 1−D

(13)

The equation reaches its maximum value, IOUT/2, when D = 0.5 Losses depend on the input capacitor ESR:

P=ESR⋅IRMS2

(14)

A6727B

Output capacitors

DS14159 - Rev 2

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