Compensation goal is to close the control loop assuring high DC regulation accuracy, good dynamic

performances and stability. To achieve this, the overall loop needs high DC gain, high bandwidth and good phase

margin.

The loop bandwidth (F0dB) can be fixed choosing the right RF/RFB ratio, however, it should not exceed FSW/2p. To

achieve a good phase margin, the control loop gain has to cross 0 dB axis with -20 dB/decade slope.

Figure 9 shows an asymptotic bode plot of a type III compensation.

Figure 9. Example of type III compensation.

Gain

[dB]

Log (Freq)

0dB

open loop

EA gain

closed

loop gain

compensation

gain

open loop

converter gain

F

LC

F

ESR

F

Z1 FZ2

F

P1

F

P2

20 log (R

F /RFB)

20 log (V

IN /∆VOSC )

F

0dB

AM16773v1

•

Open loop converter singularities:

a)

FLC= 1

2π L⋅COUT

(5)

b)

FESR= 1

2π⋅COUT⋅ESR

•

Compensation network singularity frequencies are:

a)

FZ1= 12π⋅RF⋅CF

(6)

b)

FZ2= 1

2π⋅ RFB+RS ⋅CS

c)

FP1= 1

2π⋅RF⋅ CF⋅CP

CF+CP

d)

FP2= 12π⋅RS⋅CS

A6727B

Compensation network

DS14159 - Rev 2

page 13/26