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AT25DF321A bảng dữ liệu(PDF) 44 Page - Renesas Technology Corp |
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AT25DF321A bảng dữ liệu(HTML) 44 Page - Renesas Technology Corp |
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44 / 51 page ![]() 44 3686I–DFLASH–02/2019 AT25DF321A Notes: 1. Not 100% tested (value guaranteed by design and characterization) 2. 15pF load at frequencies above 70MHz, 30pF otherwise 3. Only applicable as a constraint for the Write Status Register Byte 1 command when SPRL = 1 Note: 1. Maximum values indicate worst-case performance after 100,000 erase/program cycles 2. Not 100% tested (value guaranteed by design and characterization) 14.8 Input Test Waveforms and Measurement Levels t EDPD (1) Chip Select High to Deep Power-Down 1 µs tRDPD (1) Chip Select High to Standby Mode 30 µs t RST Reset Time 30 µs 14.6 Program and Erase Characteristics Symbol Parameter Min Typ Max Units tPP (1) Page Program Time (256-Bytes) 1.0 3.0 ms t BP Byte Program Time 7 µs tBLKE (1) Block Erase Time 4-Kbytes 50 200 ms 32-Kbytes 250 600 64-Kbytes 400 950 t CHPE (1)(2) Chip Erase Time 25 40 sec tSUSP Suspend Time Program 10 20 µs Erase 25 40 t RES Resume Time Program 10 20 µs Erase 12 20 t OTPP (1) OTP Security Register Program Time 200 500 µs t WRSR (2) Write Status Register Time 200 ns 14.7 Power-up Conditions Symbol Parameter Min Max Units tVCSL Minimum VCC to Chip Select Low Time 70 µs t PUW Power-up Device Delay Before Program or Erase Allowed 10 ms V POR Power-on Reset Voltage 1.5 2.5 V 14.5 AC Characteristics – All Other Parameters (Continued) Symbol Parameter Min Max Units AC DRIVING LEVELS AC MEASUREMENT LEVEL 0.1V CC V CC/2 0.9V CC tR, tF < 2 ns (10% to 90%) |
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