VL53L8CXV0GCSLASH1 datasheet(10/42 Pages) STMICROELECTRONICS

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2.3

Power up sequence

The VL53L8CX requires three power supplies:

•

CORE_1V8: Analog core supply fixed at 1.8 V.

•

AVDD: Analog and VCSEL supply fixed at 3.3 V.

•

IOVDD: Voltage supply to the IO, which may be either 1.2 V or 1.8 V depending on the system it is

integrating with. If IOVDD is 1.8 V, then the same supply may be used for both IOVDD and CORE_1V8.

When powering up the device, the three supplies should be applied at the same time.

When powering down the device, the three supplies should be removed at the same time.

To ensure proper operation of the module, the following minimum slew rates on the supplies (see Figure 9. Power

up slew) must be met. This ensures correct operation of the power on the reset circuitry. The circuitry triggers

at 0.9 V. However, the supplies should reach their operation levels in accordance with the slew rates listed in

Table 5. Supply slew minimum limits.

Figure 9. Power up slew

Note:

The minimum reset time is the minimum time required for the device RAM to load and boot up after CORE_1V8

reaches the power-on reset rising threshold. The supply must have reached the minimum operating level (1.6 V)

within this time.

Note:

The AVDD rise time is determined by the internal analog levels, which must be stable for correct operation.

Note:

CORE_1V8 and IOVDD are assumed to be the same supply (1V8) in Figure 9. Power up slew. If using 1V2,

then IOVDD should be applied at the same time as the other supplies.

Table 5. Supply slew minimum limits

Supply status

AVDD slew

CORE_1V8 slew

IOVDD slew

Start together

0.001 V/µs

0.012 V/µs

AVDD stable followed by

CORE_1V8 and IOVDD

—

0.012 V/µs

CORE_1V8 stable followed

by AVDD and IOVDD

0.001 V/µs

—

0.012 V/µs

IOVDD stable followed by

AVDD and CORE_1V8

0.001 V/µs

0.012 V/µs

—

VL53L8CX

Power up sequence

DS14161 - Rev 2

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