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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DS0128 bảng dữ liệu(PDF) 99 Page - Microsemi Corporation |
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DS0128 bảng dữ liệu(HTML) 99 Page - Microsemi Corporation |
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99 / 140 page  IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 89 The following table lists the µSRAM in 128 × 8 mode in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Read asynchronous reset removal time (pipelined clock) TRSTREM –0.023 –0.027 ns Read asynchronous reset removal time (non-pipelined clock) 0.046 0.054 ns Read asynchronous reset recovery time (pipelined clock) TRSTREC 0.507 0.597 ns Read asynchronous reset recovery time (non-pipelined clock) 0.236 0.278 ns Read asynchronous reset to output propagation delay (with pipelined register enabled) TR2Q 0.835 0.982 ns Read synchronous reset setup time TSRSTSU 0.271 0.319 ns Read synchronous reset hold time TSRSTHD 0.061 0.071 ns Write clock period TCCY 44 ns Write clock minimum pulse width high TCCLKMPWH 1.8 1.8 ns Write clock minimum pulse width low TCCLKMPWL 1.8 1.8 ns Write block setup time TBLKCSU 0.404 0.476 ns Write block hold time TBLKCHD 0.007 0.008 ns Write input data setup time TDINCSU 0.115 0.135 ns Write input data hold time TDINCHD 0.15 0.177 ns Write address setup time TADDRCSU 0.088 0.104 ns Write address hold time TADDRCHD 0.128 0.15 ns Write enable setup time TWECSU 0.397 0.467 ns Write enable hold time TWECHD –0.026 –0.03 ns Maximum frequency FMAX 250 250 MHz Table 240 • µSRAM (RAM128x8) in 128 × 8 Mode Parameter Symbol –1 –Std Unit Min Max Min Max Read clock period TCY 44 ns Read clock minimum pulse width high TCLKMPWH 1.8 1.8 ns Read clock minimum pulse width low TCLKMPWL 1.8 1.8 ns Read pipeline clock period TPLCY 44 ns Read pipeline clock minimum pulse width high TPLCLKMPWH 1.8 1.8 ns Read pipeline clock minimum pulse width low TPLCLKMPWL 1.8 1.8 ns Read access time with pipeline register TCLK2Q 0.266 0.313 ns Read access time without pipeline register 1.677 1.973 ns Read address setup time in synchronous mode TADDRSU 0.301 0.354 ns Read address setup time in asynchronous mode 1.856 2.184 ns Table 239 • µSRAM (RAM128x9) in 128 × 9 Mode (continued) Parameter Symbol –1 –Std Unit Min Max Min Max |
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