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DS0128 bảng dữ liệu(PDF) 101 Page - Microsemi Corporation |
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DS0128 bảng dữ liệu(HTML) 101 Page - Microsemi Corporation |
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101 / 140 page  IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 91 The following table lists the µSRAM in 256 × 4 mode in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Table 241 • µSRAM (RAM256x4) in 256 × 4 Mode Parameter Symbol –1 –Std Unit Min Max Min Max Read clock period TCY 44 ns Read clock minimum pulse width high TCLKMPWH 1.8 1.8 ns Read clock minimum pulse width low TCLKMPWL 1.8 1.8 ns Read pipeline clock period TPLCY 44 ns Read pipeline clock minimum pulse width high TPLCLKMPWH 1.8 1.8 ns Read pipeline clock minimum pulse width low TPLCLKMPWL 1.8 1.8 ns Read access time with pipeline register TCLK2Q 0.27 0.31 ns Read access time without pipeline register 1.75 2.06 ns Read address setup time in synchronous mode TADDRSU 0.301 0.354 ns Read address setup time in asynchronous mode 1.931 2.272 ns Read address hold time in synchronous mode TADDRHD 0.121 0.142 ns Read address hold time in asynchronous mode –0.65 –0.76 ns Read enable setup time TRDENSU 0.278 0.327 ns Read enable hold time TRDENHD 0.057 0.067 ns Read block select setup time TBLKSU 1.839 2.163 ns Read block select hold time TBLKHD –0.65 –0.77 ns Read block select to out disable time (when pipelined register is disabled) TBLK2Q 2.09 2.46 ns Read asynchronous reset removal time (pipelined clock) TRSTREM –0.02 –0.03 ns Read asynchronous reset removal time (non-pipelined clock) 0.046 0.054 ns Read asynchronous reset recovery time (pipelined clock) TRSTREC 0.507 0.597 ns Read asynchronous reset recovery time (non-pipelined clock) 0.236 0.278 ns Read asynchronous reset to output propagation delay (with pipelined register enabled) TR2Q 0.83 0.98 ns Read synchronous reset setup time TSRSTSU 0.271 0.319 ns Read synchronous reset hold time TSRSTHD 0.061 0.071 ns Write clock period TCCY 44 ns Write clock minimum pulse width high TCCLKMPWH 1.8 1.8 ns Write clock minimum pulse width low TCCLKMPWL 1.8 1.8 ns Write block setup time TBLKCSU 0.404 0.476 ns Write block hold time TBLKCHD 0.007 0.008 ns Write input data setup time TDINCSU 0.101 0.118 ns Write input data hold time TDINCHD 0.137 0.161 ns Write address setup time TADDRCSU 0.088 0.104 ns |
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