PAC1941T-1ESLASH4MX. datasheet(68/96 Pages) MICROCHIP

68 / 96 page

PAC194X

DS20006543A-page 68

 2021 Microchip Technology Inc.

ACC FULLNESS LIMITS (29H) REGISTER

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

R/W-1

CH1 ACC FULL[1:0]

CH2 ACC FULL[1:0]

CH3 ACC FULL[1:0]

CH4 ACC FULL[1:0]

bit 15

bit 8

R/W-0

R/W-1

U-0

ACC COUNT FULL[1:0]

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

These limits are used to set a limit for how full the Accumulators and Accumulator Count registers can be before the

Accumulator Full and Accumulator Count full limits are tripped. This allows an ALERT to be registered when the

Accumulator and Accumulator Count are approaching 100% full. Disable ALERTs in Register 7-34 before changing

the value to avoid false triggers.

bit 15-14

CH1 ACC FULL[1:0]: Fullness limit for the Channel 1 Accumulator:

00 = Full

01 = 15/16 full (default)

10 = 7/8 full

11 = 3/4 full

bit 13-12

CH2 ACC FULL[1:0]: Fullness limit for the Channel 2 Accumulator:

00 = Full

01 = 15/16 full (default)

10 = 7/8 full

11 = 3/4 full

bit 11-10

CH3 ACC FULL[1:0]: Fullness limit for the Channel 3 Accumulator:

00 = Full

01 = 15/16 full (default)

10 = 7/8 full

11 = 3/4 full

bit 9-8

CH4 ACC FULL[1:0]: Fullness limit for the Channel 4 Accumulator:

00 = Full

01 = 15/16 full (default)

10 = 7/8 full

11 = 3/4 full

bit 7-6

ACC COUNT FULL[1:0]: Fullness limit for the Accumulator Count register:

00 = Full

01 = 15/16 full (default)

10 = 7/8 full

11 = 3/4 full

bit 5-0

Unimplemented, read as ‘0’.

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