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PAC1941T-1E/4MX. bảng dữ liệu(PDF) 33 Page - Microchip Technology

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DS20006543A-page 33
PAC194X
6.0
SMBUS AND I2C
COMMUNICATIONS
PROTOCOL
The PAC194X devices communicate over a two-wire
bus with a controller, using a SMBus or I2C serial com-
munication protocol. A detailed timing diagram is
shown in Figure 6-1.
Stretching of the SMCLK signal is supported.
However, the PAC194X will not stretch the clock signal
itself.
FIGURE 6-1:
SMBus Timing Diagram.
6.1
I2C/SMBus Addressing and
Control Bits
6.1.1
SMBUS ADDRESS AND RD/WR BIT
The SMBus Address byte consists of the 7-bit client
address followed by a 1-bit RD/WR indicator. If this
RD/WR bit is a logic ‘0’, the SMBus host writes data to
the client device. If this RD/WR bit is a logic ‘1’, the
SMBus host reads data from the client device.
The PAC194X I2C/SMBus address is determined by a
single pull-down resistor connected between ground
and the ADDRSEL pin, as shown in Table 6-1. The
chip translates the resistor value into an address on
power-up and the value is latched until another
power-up event takes place. The address cannot be
changed on the fly.
6.1.2
SMBUS START BIT
The SMBus Start bit is defined as a transition of the
SMBus data line from a logic ‘1’ state to a logic ‘0’
state, while the SMBus clock line is in a logic ‘1’ state.
6.1.3
SMBUS ACK AND NACK BITS
The SMBus client will ACK (acknowledge) all data
bytes that it receives. This is done by the client device
pulling the SMBus data line low after the eighth bit of
each byte that is transmitted.
6.1.4
SMBUS STOP BIT
The SMBus Stop bit is defined as a transition of the
SMBus data line from a logic ‘0’ state to a logic ‘1’
state, while the SMBus clock line is in a logic ‘1’ state.
When the PAC194X detects an SMBus Stop bit and it
has been communicating with the SMBus protocol, it
resets its client interface and prepares to receive
further communications.
SMDATA
SMCLK
T
BUF
P
S
S - Start Condition
P - Stop Condition
P
S
T HIGH
T LOW
T
HD:STA
T
SU:STO
T
HD:STA
T
HD:DAT
T
SU:DAT
T
SU:STA
T
FALL
T
RISE



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