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HC705V8GRS/D bảng dữ liệu(PDF) 91 Page - NXP Semiconductors |
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HC705V8GRS/D bảng dữ liệu(HTML) 91 Page - NXP Semiconductors |
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91 / 172 page ![]() SECTION 11: 16-BIT TIMER Page 80 MC68HC705V8 Specification Rev. 2.1 The counter alternate register at address $1A and $1B contains the same value as the free- running counter (at address $18 and $19); therefore, this alternate register can be read at any time without affecting the timer overflow flag in the timer status register. 11.6 TIMER DURING WAIT MODE The CPU clock halts during the WAIT mode, but the timer remains active if turned on prior to entering wait mode. If interrupts are enabled, a timer interrupt will cause the processor to exit the WAIT mode. 11.7 TIMER DURING STOP MODE In the STOP mode, the timer stops counting and holds the last count value if STOP is exited by an interrupt. If RESET is used, the counter is forced to $FFFC. During STOP, if the TIMER is on and at least one valid input capture edge occurs at the TCAP pin, the input capture detect circuit is armed. This does not set any timer flags nor wake up the MCU, but when the MCU does wake up, there is an active input capture flag and data from the first valid edge that occurred during the STOP mode. If RESET is used to exit STOP mode, then no input capture flag or data remains, even if a valid input capture edge occurred. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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